Semiconductor Storage Device Interconnect Architecture
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Solution Overview
Problem
The miniaturization of semiconductor storage devices poses challenges in reducing the circuit area while maintaining efficient signal transmission and voltage distribution, leading to increased complexity and size in NAND-type flash memory systems.
Innovation Solution
The implementation of interconnects in the fourth metal layer above the bit line hookup circuit, which are not directly connected to the circuit, allows for reduced circuit area by routing first and second column control signals, voltage transfer, and word line drive signals, thereby minimizing the overall size of the NAND-type flash memory system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional signal and voltage transmission methods are used, then reliable signal transmission is achieved, but the circuit area increases
Solution Approach 1:
The patent utilizes a fourth metal layer positioned above the bit line hookup circuit to route interconnects for column control signals, voltage transfer, and word line drive signals. This vertical stacking approach (adding the Z-dimension) allows multiple signal paths to coexist without increasing the planar footprint, thereby reducing circuit area while maintaining reliable signal transmission through dedicated interconnect layers.
2Adaptability or versatility
If more interconnects are added for signal routing, then signal transmission capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the interconnect structure by function and layer: the fourth metal layer is dedicated to non-directly-connected interconnects for column control signals and voltage transfer, while lower metal layers handle directly-connected circuit interconnects. This segmentation allows complex signal routing capabilities to be achieved through organized, modular interconnect layers, reducing overall device complexity despite the increased number of interconnects.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes: a memory cell array including a plurality of bit lines; a sense amplifier; a first circuit including a plurality of transistors respectively connected to the plurality of bit lines and the sense amplifier; and a plurality of interconnects which are provided at a position higher than the bit lines in the first circuit and are not directly connected to the first circuit. The semiconductor storage device does not include, at a position higher than the plurality of interconnects, an interconnect which electrically connects two positions in the semiconductor storage device.