Semiconductor Storage Device Multiplexer Area Reduction via Dummy Signal Lines
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Solution Overview
Problem
The increasing number of bit lines or word lines in semiconductor storage devices leads to a larger area occupied by decoders, and omitting transistors in multiplexers risks incorrect selection voltage application to unselected lines, affecting adjacent lines and increasing heat transfer.
Innovation Solution
A semiconductor storage device configuration with global signal lines, transistors, and dummy signal lines that apply selection and non-selection voltages to specific groups of bit or word lines, reducing area requirements and minimizing voltage fluctuations and heat transfer to unselected lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bit lines or word lines is increased to expand storage capacity, then the storage capacity is improved, but the area occupied by the decoder is increased
Solution Approach 1:
The patent divides the bit lines into multiple groups (first group, second group, third group, fourth group) and uses separate multiplexers for each group. This segmentation allows the decoder to be divided into smaller units, reducing the area occupied by each individual multiplexer while maintaining the ability to select any bit line in the expanded storage capacity system.
2Area of stationary object
If transistors in the multiplexer are omitted to reduce area, then the multiplexer area is reduced, but selection voltage may be wrongly applied to unselected lines
Solution Approach 1:
The patent applies different voltage levels to different groups of bit lines based on their selection state. Selected bit lines receive a first voltage level, unselected bit lines receive a second voltage level, and adjacent unselected bit lines receive a third voltage level. This local differentiation of voltage quality ensures that even without additional transistors, each bit line group receives the appropriate voltage for its state, preventing wrong voltage application.
Solution Approach 2:
The patent introduces dummy bit lines as intermediary elements between adjacent bit line groups. These dummy bit lines act as buffers that prevent voltage fluctuations in selected bit lines from directly affecting adjacent unselected bit lines, thereby maintaining voltage selection accuracy without requiring additional transistors in the multiplexer structure.
3Area of stationary object
If transistors are omitted to reduce area, then the multiplexer area is reduced, but heat may affect adjacent unselected lines
Solution Approach 1:
The patent introduces dummy bit lines as intermediary elements between adjacent bit line groups. These dummy bit lines act as thermal and electrical buffers that prevent heat generated in selected bit lines from directly transferring to adjacent unselected bit lines, thereby reducing heat-related harmful effects without requiring additional transistors.
Data Source
AI summary
A semiconductor storage device includes first signal lines divided into groups respectively including m (m is an integer equal to or larger than 2) of the first signal lines; and second signal lines. A memory cell array includes memory cells provided to correspond to respective intersections of the first signal lines and the second signal lines. A selection voltage is applied to any of the first signal lines through m global signal lines. First transistors are provided to respectively correspond to the first signal lines and connected between the first signal lines and the global signal lines. First selection signal lines are provided to respectively correspond to the groups and connected to gate electrodes of the first transistors included in a corresponding one of the groups in common. First dummy signal lines are arranged between adjacent ones of the groups, to which a non-selection voltage is applied.