Semiconductor Memory Device Storage Node Contact Spacer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in achieving reliable electrical characteristics due to the formation of dangling bonds at the interface between polysilicon and silicon nitride, leading to depletion and reduced contact area, which affects their reliability and performance.
Innovation Solution
A dielectric pattern made of silicon oxide or hafnium oxide is interposed between the storage node contact and the second spacer, preventing the formation of dangling bonds and reducing depletion at the storage node contact, thereby enhancing the reliability and electrical characteristics of the semiconductor memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bit-line spacer is formed between the bit line and storage node contact, then electrical connection is improved, but dangling bonds form at the polysilicon-silicon nitride interface causing depletion and reduced contact area
Solution Approach 1:
A dielectric pattern (intermediary layer) is introduced between the bit-line spacer and storage node contact to prevent direct contact between polysilicon and silicon nitride, thereby eliminating the formation of dangling bonds at their interface while maintaining electrical connection reliability
Solution Approach 2:
The harmful interface between polysilicon and silicon nitride is extracted or separated by removing the direct contact between these two materials through the introduction of the dielectric pattern, eliminating the source of dangling bonds and depletion
2Ease of manufacture
If polysilicon and silicon nitride are in direct contact, then manufacturing is simplified, but depletion occurs reducing effective contact area and electrical characteristics
Solution Approach 1:
The dielectric pattern serves as an intermediary layer that prevents direct contact between polysilicon and silicon nitride, maintaining manufacturing feasibility while precisely controlling the contact area to prevent depletion and ensure reliable electrical characteristics
Data Source
AI summary
A semiconductor memory device includes a substrate including a device isolation pattern defining an active pattern extending in a first direction and including first and second source/drain regions, a word line extending in a second direction intersecting the first direction, a bit line that is on the word line and electrically connected to the first source/drain region and that extends in a third direction that intersects the first and second directions, a bit-line spacer on a sidewall of the bit line, a storage node contact electrically connected to the second source/drain region and spaced apart from the bit line across the bit-line spacer, and a dielectric pattern between the bit-line spacer and the storage node contact. The bit-line spacer includes a first spacer covering the sidewall of the bit line and a second spacer between the dielectric pattern and the first spacer.