Semiconductor Storage Node Contact Hole Etching via Landing Plug
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reducing chip size due to issues with buried gate structures, such as increased cell area, leakage current, and difficulties in patterning small contact holes during etching, which lead to contact resistance problems and the need for Self-Aligned Contact (SAC) processes.
Innovation Solution
The method involves forming a sufficiently large storage node contact hole to facilitate etching with a small Critical Dimension (CD), using a landing plug to reduce resistance, and performing the SAC process during bit line formation, along with selective epi growth to increase junction region height and reduce Gate Induced Drain Leakage (GIDL), and employing a damascene process for bit line formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a buried gate structure is used to reduce chip size, then the number of transistors per chip increases, but the cell area becomes larger and leakage current increases
Solution Approach 1:
The patent transitions from a planar gate structure to a vertically-oriented buried gate structure formed in a recess. The gate extends downward into the substrate, utilizing the vertical dimension to achieve higher transistor density without proportionally increasing the horizontal cell area. This dimensional change allows more transistors to be packed into each chip while maintaining reasonable cell footprint.
2Productivity
If a buried gate structure with trench-type device isolation film is used, then chip size is reduced, but contact hole patterning becomes difficult and contact resistance increases
Solution Approach 1:
The patent performs preliminary actions by forming the buried gate structure and device isolation films before forming the contact holes. The recess structure is pre-formed with the gate embedded, and device isolation films are deposited and planarized in advance. This preliminary preparation creates a more favorable geometry for subsequent contact hole etching, allowing better pattern definition and etch access compared to forming contacts after the buried gate is complete.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions: the device isolation films have specific dielectric properties tailored for electrical isolation, while the recess structure provides localized mechanical support and electrical field confinement. These localized quality adjustments optimize both the patterning process and the final electrical performance of contact holes in the buried gate structure.
3Productivity
If the Critical Dimension is reduced to enable smaller contact holes, then chip density increases, but the contact hole pattern cannot be defined on the mask and etching fails
Solution Approach 1:
The patent performs preliminary actions by forming the buried gate structure and device isolation films before forming the contact holes. The recess structure is pre-formed with the gate embedded, and device isolation films are deposited and planarized in advance. This preliminary preparation creates a more favorable geometry for subsequent contact hole etching, allowing better pattern definition and etch access compared to forming contacts after the buried gate is complete.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the successful etching of storage node contact holes with small CD without requiring SAC, lowers plug resistance, and reduces GIDL, thereby improving the fabrication of semiconductor devices by eliminating the need for SAC during bit line formation and enhancing device performance.
Implementation Method 1
selective epi growth to increase junction region height and reduce Gate Induced Drain Leakage (GIDL)
Implementation Method 2
implanting ions into the landing plug
Data Source
AI summary
The invention relates to a semiconductor device, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance. A semiconductor device according to the invention comprises: first and second active regions formed in a substrate, the first and second active being adjacent to each other, each of the first and second active regions including a bit-line contact region and a storage node contact region and a device isolation structure; a word line provided within a trench formed in the substrate; first and second storage node contact plugs assigned to the first and second active regions, respectively, the first and second storage node contact plugs being separated from each other by a bit line groove; and a bit line formed within the bit-line groove.