Semiconductor Storage Node Contact Plug Spacer Design
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Solution Overview
Problem
The integration of semiconductor memory devices is limited by the need for expensive equipment to pattern devices at desired sizes, which hinders increased density and higher performance at affordable prices.
Innovation Solution
A semiconductor device design that includes a substrate with doped regions, storage node contact plugs, bit line connections, and spacers with etch stop patterns and sub-spacers, which improve electrical isolation and reduce leakage current through the use of air-gap regions and materials with etch selectivity, allowing for more efficient fabrication and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning equipment is used to fabricate semiconductor devices, then manufacturing precision can be maintained, but device integration density is limited and fabrication cost increases
Solution Approach 1:
The fabrication process is segmented into multiple self-aligned steps: forming mandrels, depositing first spacers, forming second mandrels, depositing second spacers, and forming air gaps. Each step builds upon the previous one with automatic alignment, enabling high integration density without requiring advanced lithography equipment.
Solution Approach 2:
The invention transitions from planar patterning to three-dimensional structure formation using vertical spacers and air gaps. The spacer layers extend in the vertical dimension, allowing increased device density without improving lateral lithography resolution.
2Productivity
If device size is reduced to increase integration density, then productivity improves, but manufacturing precision requirements increase and cost increases
Solution Approach 1:
The spacers serve as self-aligned masks for subsequent etching steps. The spacer width is determined by conformal deposition thickness rather than lithography, and the air gaps provide self-aligned isolation. This self-service mechanism eliminates the need for high-precision lithography to define small features.
3Productivity
If integration density is increased, then productivity improves, but leakage current increases and electrical characteristics deteriorate
Solution Approach 1:
Air gaps are introduced as intermediary regions between adjacent conductive structures (bit lines, contact plugs). These air gaps provide electrical isolation and reduce parasitic capacitance and leakage current between closely spaced devices, enabling high integration without sacrificing electrical performance.
Data Source
AI summary
Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed.