Semiconductor Storage Node Hole Formation via Bowing Prevention Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge is to increase the capacitance of capacitors in semiconductor devices while maintaining a limited area, as capacitance is proportional to the surface area of electrodes and dielectric constant, but inversely proportional to the equivalent thickness of the dielectric layer, requiring innovative manufacturing methods to enhance electrode surface area and reduce dielectric layer thickness.
Innovation Solution
A semiconductor device manufacturing method involving the sequential formation of layers, including a bowing prevention layer and support layers, using dry and wet etching processes to form storage node holes and electrodes, where the bowing prevention layer has a higher etch rate during wet etching, allowing for the removal of layers while maintaining structural integrity and increasing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the surface area of electrodes is increased to enhance capacitance, then capacitance is improved, but device area is exceeded
Solution Approach 1:
The patent transitions from planar electrodes to three-dimensional hollow cylindrical electrodes with radial extensions. The lower electrode includes a radial extension that protrudes into the storage node hole, and the upper electrode has a corresponding radial extension, creating a multi-dimensional electrode structure that increases surface area without proportionally increasing device footprint.
Solution Approach 2:
The patent implements nested electrode structures where the lower electrode's radial extension is positioned within the storage node hole, and the upper electrode's radial extension surrounds it. The dielectric layer is conformally deposited on these nested structures, creating a multi-layer nested configuration that maximizes electrode surface area within the vertical dimension.
2Quantity of substance
If the equivalent thickness of dielectric layer is reduced to increase capacitance, then capacitance is improved, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The patent performs preliminary patterning of the upper support layer and bowing prevention layer to expose the upper mold layer before dielectric deposition. This preliminary action creates a defined template that guides subsequent conformal dielectric layer formation, ensuring uniform thickness control even for thin dielectric layers.
Solution Approach 2:
The patent replaces mechanical thickness control methods with chemical vapor deposition or atomic layer deposition processes for dielectric layer formation. These deposition methods provide atomic-level thickness control through process parameters rather than mechanical means, enabling precise control of thin dielectric layers.
3Manufacturing precision
If dry etching is used to form storage node holes, then manufacturing precision is improved, but bowing phenomenon occurs in support layers
Solution Approach 1:
The patent introduces a bowing prevention layer as an intermediary between the upper support layer and upper mold layer. This intermediate layer has different etch selectivity and mechanical properties that prevent stress transfer during dry etching, thereby preventing bowing of the support layer while allowing precise storage node hole formation.
Solution Approach 2:
The patent modifies the etch selectivity parameters by using a bowing prevention layer with specific material composition (silicon nitride or silicon oxynitride) that has different etch rates compared to the support layer. This parameter change in etch selectivity allows the support layer to maintain flatness while the mold layer is etched with high precision.
4Stability of the object's composition
If multiple layers are formed to prevent bowing, then structural integrity is improved, but device complexity increases
Solution Approach 1:
The patent segments the upper support structure into multiple functional layers: upper support layer, bowing prevention layer, and upper mold layer. Each layer has a specific thickness and material composition optimized for its function, allowing the complex structure to be manufactured through sequential deposition and etching processes rather than requiring a single complex component.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively increases capacitance by optimizing the thickness and etch rates of layers, preventing bowing phenomena during dry etching and enhancing capacitance through controlled wet etching, thereby improving the performance of capacitors in semiconductor devices.
Implementation Method 1
forming a storage node hole passing through the upper support layer, the bowing prevention layer and the upper mold layer by using a dry etching process
Implementation Method 2
removing the upper mold layer and at least a portion of the bowing prevention layer using a first wet etching process
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a storage node hole passing through an upper support layer, a bowing prevention layer and an upper mold layer using a dry etching process, forming a lower electrode in the storage node hole, patterning the upper support layer and the bowing prevention layer to expose a portion of the upper mold layer, removing the upper mold layer and at least a portion of the bowing prevention layer using a first wet etching process, and sequentially forming a dielectric layer and an upper electrode that cover the lower electrode. An etch rate of the bowing prevention layer may be substantially equal to an etch rate of the upper support layer during the dry etching process. An etch rate of the bowing prevention layer may be higher than an etch rate of the upper support layer during the first wet etching process.