Semiconductor Storage Device With Non-Uniform Conductive Layer Spacing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor storage devices face challenges in achieving high integration and uniform voltage transfer speed among stacked conductive layers, with existing configurations resulting in varying wiring resistances and capacitances that affect performance.
Innovation Solution
The semiconductor storage device incorporates a semiconductor layer with varying widths and conductive layers arranged at specific intervals, with the semiconductor layer having a smaller outer diameter at the lower part and a larger outer diameter at the upper part, and conductive layers spaced at different intervals to optimize wiring resistance and capacitance, allowing for high integration and uniform voltage transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive layers are arranged at equal intervals, then the structure is simple and easy to manufacture, but the wiring resistance varies among layers affecting voltage transfer uniformity
Solution Approach 1:
The patent applies local quality by varying the intervals between conductive layers at different positions. Specifically, the interval between adjacent conductive layers is made smaller at the lower part (closer to substrate) and larger at the upper part. This non-uniform spacing compensates for the increased capacitance and resistance at lower layers, achieving uniform voltage transfer speed across all layers while maintaining a manageable structural complexity.
2Productivity
If semiconductor layer has uniform width, then the manufacturing process is simpler, but the wiring resistance and capacitance cannot be optimized for high integration
Solution Approach 1:
The semiconductor layer is designed with varying width along the first direction, creating different regions (first, second, and third regions) with different cross-sectional areas. This allows optimization of electrical properties in different zones to reduce wiring resistance and increase integration density, while the width variation is achieved through standard photolithography and etching processes, maintaining reasonable manufacturing simplicity.
3Volume of moving object
If conductive layers are placed closer together, then the device size is reduced for high integration, but the capacitance between layers increases affecting signal integrity
Solution Approach 1:
The patent changes the spacing parameter between conductive layers dynamically rather than keeping it constant. By making the interval smaller at the lower part and larger at the upper part, the design optimizes the balance between device compactness and capacitance control. This parameter variation allows high integration density while preventing excessive capacitance that would degrade signal integrity.
Data Source
AI summary
A semiconductor storage device includes a substrate, a plurality of conductive layers arranged in a first direction intersecting a surface of the substrate, and a semiconductor layer extending in the first direction and penetrating the plurality of conductive layers. The plurality of conductive layers includes a first conductive layer and a second conductive layer that are adjacent to each other, a third conductive layer and a fourth conductive layer that are adjacent to each other, and a fifth conductive layer and a sixth conductive layer that are adjacent to each other. When a distance between the first conductive layer and the second conductive layer in the first direction is a first distance, a distance between the third conductive layer and the fourth conductive layer in the first direction is a second distance, and a distance between the fifth conductive layer and the sixth conductive layer in the first direction is a third distance, the second distance is smaller than the first distance, and the third distance is smaller than the second distance.