Semiconductor Storage Device Non-Zero Bit Line Potential Control
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Solution Overview
Problem
As semiconductor storage devices integrate more memory cells, power consumption increases due to frequent reading and writing operations, especially in machine learning applications like updating weight coefficients in neural networks, where product-sum operations are repetitive and power-intensive.
Innovation Solution
A semiconductor storage device design that includes multiple memory cells arranged in a direction with specific wiring pairs to perform product-sum operations efficiently, where potentials on second bit line pairs are changed only when the addition result of multiplication data is non-zero, reducing unnecessary power consumption by minimizing changes when the result is zero.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration degree of memory cells is increased, then the storage capacity and processing capability are improved, but the power consumption increases
Solution Approach 1:
The patent changes the operational parameter of the bit line from always changing potential to only changing potential when the addition result is non-zero. This parameter change in the control logic reduces the frequency of potential changes, thereby lowering power consumption while maintaining the high integration degree of memory cells
Solution Approach 2:
The patent implements conditional periodic action where potential changes on bit lines occur only periodically when necessary (when addition results are non-zero) rather than continuously. This selective periodic operation reduces unnecessary power consumption during repetitive product-sum operations in machine learning workloads
2Measurement precision
If the number of updates of weight coefficients is increased, then the machine learning accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent modifies the control parameter of bit line potential changes to occur only when addition results are non-zero. This enables multiple weight coefficient updates for improved machine learning accuracy while reducing power consumption by eliminating unnecessary potential changes during updates
3Productivity
If the number of product-sum operation processing is increased, then the machine learning speed is improved, but the power consumption increases
Solution Approach 1:
The patent implements conditional periodic action where bit line potential changes occur only when addition results are non-zero during product-sum operations. This allows high-speed machine learning processing through multiple operations while reducing power consumption by skipping unnecessary potential changes in repetitive operations
Solution Approach 2:
The patent changes the operational parameter from continuous potential changes to conditional potential changes based on addition results. This parameter modification enables faster product-sum operation processing while reducing power consumption by minimizing unnecessary electrical transitions
Data Source
AI summary
A semiconductor storage device has a plurality of memory cells that are arranged in a first direction and store first data, a plurality of first wiring pairs that are provided corresponding to the plurality of memory cells arranged in the first direction, and supply second data multiplied with the first data, a second wiring pair that is provided corresponding to two memory cells adjacent to each other in the first direction, and outputs multiplication data obtained by multiplying the first data stored in the two memory cells with the corresponding second data on the first wiring pair, and a third wiring pair in which potentials are changed depending on an addition result only when the addition result obtained by adding two multiplication data output to the second wiring pair to each other is not zero.