Semiconductor Storage Device Output Buffer Impedance Control

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Solution Overview

Problem

Semiconductor storage devices face reliability issues due to variations in transistor size affecting output impedance, leading to deviations in signal timing and reduced communication speed.

Innovation Solution

The semiconductor storage device includes a configuration with multiple pre-drivers and output buffers, where transistor sizes are adjusted based on Ron information to optimize output impedance, ensuring consistent signal timing and improved reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If transistor sizes are standardized, then manufacturing process is simplified, but output impedance variations increase leading to signal timing deviations

Engineering Contradiction:

Improvetransistor size standardizationVSAvoidsignal timing consistency

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent applies parameter changes by adjusting transistor sizes in pre-drivers based on measured output impedance characteristics. Specifically, transistor sizes are modified to compensate for impedance variations, thereby maintaining consistent signal timing across different devices while still allowing manufacturing flexibility

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback through output impedance measurement and subsequent pre-driver adjustment. The measured impedance data is used to determine appropriate transistor size modifications, creating a closed-loop system that ensures signal timing consistency while accommodating manufacturing variations

Inventive Principle:

Principle #23Feedback

2Reliability

If transistor sizes are adjusted to optimize output impedance, then signal timing consistency improves, but device complexity increases

Engineering Contradiction:

Improvesignal timing consistencyVSAvoidtransistor size variation management

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent manages device complexity by systematically varying transistor sizes in pre-drivers based on measured output impedance. This controlled parameter adjustment optimizes signal timing consistency while maintaining design manageability through a structured approach to size modification

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies local quality by making specific transistor size adjustments only in pre-drivers where output impedance variations are detected. This targeted approach improves signal timing consistency in affected areas without unnecessarily complicating the entire device structure

Inventive Principle:

Principle #3Local quality

3Productivity

If output impedance is optimized, then communication speed improves, but manufacturing precision requirements increase

Engineering Contradiction:

Improvecommunication speedVSAvoidtransistor size control

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent uses feedback from output impedance measurements to guide pre-driver adjustments, enabling communication speed optimization without imposing stringent manufacturing precision requirements. The measured impedance data compensates for manufacturing variations, allowing faster communication while maintaining relaxed fabrication tolerances

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS10431266B2Semiconductor storage device

Publication Date: 2019.10.01 KIOXIA CORP

AI summary

A semiconductor storage device includes: a first terminal, a plurality of first and second output buffers, a register, a plurality of first pre-drivers including a plurality of first transistors operating according to a first signal, and a plurality of second pre-drivers including a plurality of second transistors operating according to a second signal. A first output control circuit selects the first pre-drivers in accordance with a third signal obtained by conversion of the second signal. A second output control circuit selects the second pre-drivers in accordance with a fourth signal obtained by conversion the first signal. A third output circuit transmits an output signal to the first and second output circuits.