Semiconductor Storage Peak Current Control via Internal State Search
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Solution Overview
Problem
In semiconductor storage devices with multiple memory chips, overlapping peak currents can lead to excessive total peak current, causing performance deterioration and inefficiencies in peak current control, as existing technologies rely on external host commands for canceling peak states, which can result in data interruption and restart issues.
Innovation Solution
A semiconductor storage device with an interface chip and memory chips that include peak counters and a peak controller, allowing for internal peak current control by searching the states of memory chips and issuing cancel instructions to manage peak current generation, thereby reducing overlapping currents without external intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external host commands are used to cancel peak states in multi-chip memory devices, then peak current control can be achieved, but data interruption and restart issues occur causing performance deterioration
Solution Approach 1:
The memory device performs self-service by implementing an internal peak current control mechanism where the control circuit monitors and manages peak currents generated by individual memory chips autonomously, eliminating the need for external host intervention and preventing data interruption
Solution Approach 2:
The control circuit employs feedback by continuously monitoring the operational state of memory chips and adjusting peak current cancellation timing based on real-time status information, ensuring optimal current management without external commands
2Device complexity
If peak current cancellation is implemented without internal management, then device complexity is reduced, but overlapping peak currents cause excessive total current and performance deterioration
Solution Approach 1:
The control circuit segments the peak current management by individually monitoring and controlling each memory chip's peak current generation, allowing precise cancellation timing for each chip to prevent overlapping without requiring complex system-wide external control
Solution Approach 2:
The control circuit acts as an intermediary between memory chips and the external host, handling peak current cancellation internally through dedicated circuitry that mediates current management without involving external commands or complex host intervention
Data Source
AI summary
In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.