Semiconductor Storage Device Pseudo Cache Program Operation
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Solution Overview
Problem
Current semiconductor storage devices face increased latency in write operations due to the limited availability of latch circuits during cache program operations, which restricts their ability to efficiently manage data transfer and processing.
Innovation Solution
The semiconductor storage device employs a pseudo cache program operation that allows the use of latch circuits in one plane while simultaneously initiating write operations on another plane, ensuring that the device remains in a ready state even during ongoing write operations by pseudo-releasing latch circuits and overlapping write data input periods with write operations, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If latch circuits are used during cache program operations, then data transfer and processing can be performed, but write operation latency increases due to limited latch circuit availability
Solution Approach 1:
The memory device is divided into multiple planes, each with independent latch circuits. This segmentation allows different planes to operate independently, enabling one plane to perform write operations while another plane's latch circuits are available for data input, thereby resolving the latency issue without sacrificing productivity
Solution Approach 2:
The system accepts a second command to carry out a write operation on a different plane before the first latch circuit is fully released. This preliminary action on an alternative plane prevents idle time and maintains continuous productivity while avoiding latch circuit conflicts
2Ease of operation
If the device remains in ready state during write operations, then it can accept new commands, but latch circuits must be pseudo-released which complicates the control logic
Solution Approach 1:
The solution moves from a single-plane time-sequential operation to a multi-plane spatial-parallel operation. By adding the plane dimension, the system can maintain ready state for command acceptance while performing write operations in parallel on different planes, managing complexity through spatial distribution rather than temporal sequencing
3Loss of time
If write data input period is overlapped with write operation, then latency is reduced, but data collision may occur in the latch circuit
Solution Approach 1:
By segmenting the memory into multiple planes with separate latch circuits, the system can overlap write data input on one plane with write operations on another plane without data collision. The segmentation provides isolated data paths that eliminate the collision risk while achieving time overlap
Solution Approach 2:
The control circuit acts as an intermediary that coordinates between different planes and latch circuits. It manages the overlapping operations by ensuring data is directed to the correct plane's latch circuit, preventing collisions while enabling parallel execution and reduced latency
Data Source
AI summary
A semiconductor storage device includes first and second planes each including a plurality of memory cells, an input/output circuit configured to receive data to be written in the memory cells from a controller, and a control circuit. The first plane includes a first sense amplifier circuit electrically connected to a first memory cell of the first plane and a first latch circuit connected in series between the input/output circuit and the first sense amplifier circuit. The control circuit is configured to carry out a first write operation on the first memory cell using the first latch circuit in response to a first command, and while carrying out the first write operation on the first memory cell, accept a second command to carry out a second write operation on a second memory cell of the second plane before use of the first latch circuit during the first write operation has ended.