Semiconductor Storage Read Circuit Bit Line Voltage Control
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Solution Overview
Problem
The miniaturization of semiconductor storage devices has led to increased bit line resistance, resulting in a reduced potential difference in charge amounts between logical values '1' and '0' during read operations, which reduces the read margin and affects the accuracy of data determination.
Innovation Solution
The semiconductor storage device employs a configuration with memory cells, reference cells, and read circuits that generate amplified signals and stop signals to determine logical values based on potential differences, ensuring the bit line voltage drops to ground potential when the stop signal reaches a threshold, thereby maintaining a sufficient read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bit line resistance increases due to miniaturization, then device integration density improves, but read margin decreases
Solution Approach 1:
The patent divides the reading process into two distinct phases: a first reading process that reads data from the memory cell, and a second reading process that reads data from reference cells. This segmentation allows each process to be optimized independently, with the second process compensating for voltage drops caused by bit line resistance in the first process.
Solution Approach 2:
Reference cells are introduced as intermediary elements that do not store actual data but provide reference voltage levels. These reference cells enable the sense amplifier to accurately determine data values by comparing against known reference levels, compensating for the effects of increased bit line resistance.
2Volume of moving object
If bit line resistance increases, then potential difference between logical values reduces, but device size decreases
Solution Approach 1:
The patent performs a preliminary reading operation from reference cells before or concurrent with the actual data reading. This preliminary action establishes reference voltage levels that account for the voltage drops caused by bit line resistance, enabling accurate measurement of the potential difference in the subsequent data reading process.
Solution Approach 2:
The patent changes the operational parameters of the memory system by introducing separate reading processes for data cells and reference cells. By adjusting the timing and sequence of these reading operations, the system compensates for the reduced potential difference caused by increased bit line resistance in miniaturized devices.
3Reliability
If gate of charge transfer circuit is not sufficiently opened due to small bit line voltage rise, then charge transfer is inadequate, but power consumption is reduced
Solution Approach 1:
The patent employs dynamic control of the charge transfer circuit gating based on the actual voltage rise detected on the bit line. The gate opening duration and timing are adjusted dynamically according to the magnitude of the voltage rise, ensuring sufficient charge transfer when needed while minimizing unnecessary operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of data determination by maintaining a sufficient read margin and preventing the reduction in potential differences between logical values, even with increased bit line resistance, ensuring accurate data reading.
Implementation Method 1
a first capacitor that accumulates charges of a first charge amount corresponding to data of a first logical value or data of a second logical value
Implementation Method 2
the charges accumulated in a capacitor are read to a bit line, and a voltage based on the charge amount is amplified by a sense amplifier
Data Source
AI summary
A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.