Semiconductor Storage Read Voltage Sequencing
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Solution Overview
Problem
Current semiconductor storage devices, such as NAND flash memory, face challenges in reducing the time required for read operations due to the complexities in voltage application and parasitic capacitance effects between word lines, which affect the convergence of voltages and increase the read operation time.
Innovation Solution
The semiconductor storage device employs a control circuit that applies specific voltage sequences to adjacent word lines during read operations, using incremental voltage adjustments and timing settings to minimize the impact of parasitic capacitance and ensure quick convergence of voltages, thereby optimizing the read operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional voltage application methods are used during read operations, then the read operation can be performed, but the time required for read operations increases due to parasitic capacitance effects and slow voltage convergence
Solution Approach 1:
The patent applies preliminary voltage adjustments to non-selected word lines before the actual read operation on the selected word line. By pre-charging or pre-discharging adjacent word lines to their target voltages, the patent reduces the voltage transition time during the read operation, thereby decreasing the overall read operation time while managing the complexity through structured voltage scheduling
Solution Approach 2:
The patent employs periodic voltage application sequences where voltages are applied in staged intervals rather than simultaneously. The control circuit applies voltages to different word lines in a timed sequence, with intermediate stabilization periods, which reduces parasitic capacitance interference and allows each word line to converge to its target voltage more quickly, thus reducing total read operation time
2Speed
If voltage is applied to selected and non-selected word lines simultaneously, then the read operation proceeds, but parasitic capacitance coupling between word lines causes slow voltage convergence and increased read time
Solution Approach 1:
The patent segments the voltage application process into distinct phases for selected and non-selected word lines. Instead of applying voltages simultaneously to all word lines, the control circuit divides them into groups and applies voltages in a staged manner, reducing the parasitic capacitance coupling effect by isolating the voltage transitions spatially and temporally, thereby improving voltage convergence speed
Solution Approach 2:
The patent applies preliminary counter-voltages or pre-charging voltages to non-selected word lines before the selected word line voltage transition. This preliminary anti-action compensates for the expected parasitic capacitance coupling effect, preventing voltage deviations and accelerating convergence by counteracting the harmful coupling before it significantly impacts the read operation
Data Source
AI summary
A semiconductor storage device includes: a first memory cell and a second memory cell that are adjacent to each other and connected to each other in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; and a control circuit. The control circuit is configured to, in a first read operation to read a first bit stored in the first memory cell, apply a first voltage to the first word line, and then, apply a first read voltage lower than the first voltage, to the first word line, and apply a second voltage to the second word line, and then, apply a third voltage lower than the second voltage and higher than the first voltage, to the second word line. The third voltage is applied to the second word line after the first read voltage is applied to the first word line.