Semiconductor Storage Device Region-Based Read Voltage Control

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Solution Overview

Problem

Current semiconductor storage devices, particularly NAND flash memories, face challenges in efficiently managing read operations across different regions of the memory cell array, leading to increased read time and potential noise due to the need to stabilize voltages across varying distances from the voltage generation circuit.

Innovation Solution

The semiconductor storage device divides the memory cell array into regions, allowing for separate control of voltages applied to word lines during read operations, ensuring rapid stabilization of read voltages in selected regions while non-selected regions are not activated, thus reducing read time and minimizing noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If voltage stabilization is performed across the entire memory cell array during read operations, then voltage stability is improved, but read time increases and noise is generated

Engineering Contradiction:
Improvevoltage stabilityVSAvoidread time
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

The memory cell array is divided into multiple regions, and voltage stabilization is performed only in the selected region during read operations rather than across the entire array. This segmentation allows rapid voltage stabilization in the active region without the time penalty of stabilizing all regions, thereby reducing read time while maintaining sufficient voltage stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the memory cell array are treated differently during read operations: the selected region receives voltage stabilization and activation, while non-selected regions remain inactive without voltage stabilization. This local quality approach ensures that resources are concentrated where needed, improving read speed without compromising the stability of the active region.

Inventive Principle:
Principle #3Local quality

2Stability of the object's composition

If voltage stabilization is performed across the entire memory cell array during read operations, then voltage stability is improved, but noise increases

Engineering Contradiction:
Improvevoltage stabilityVSAvoidnoise
Core Design Contradiction:
Stability of the object's compositionVSObject-generated harmful factors

Solution Approach 1:

By segmenting the memory cell array into multiple regions and applying voltage stabilization only to the selected region, the patent reduces the overall noise generated during read operations. The limited scope of voltage stabilization minimizes electrical interference and noise while maintaining sufficient stability in the active region.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies voltage stabilization locally only to the selected region during read operations, rather than globally across the entire array. This local quality approach reduces noise generation by limiting the scope of voltage changes and electrical activity to only where necessary, thereby minimizing harmful electromagnetic interference.

Inventive Principle:
Principle #3Local quality

3Productivity

If the memory cell array is not divided into regions, then device complexity is reduced, but read time increases

Engineering Contradiction:
Improveread speedVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory cell array is divided into multiple regions to enable faster read operations. This segmentation allows the system to quickly activate and stabilize only the necessary region during read operations, improving read speed. The region division is implemented through additional circuitry and control logic, which increases device complexity but is justified by the significant performance improvement.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240420765A1Semiconductor storage device
Publication Date: 2024.12.19 KIOXIA CORP
  • US20240420765A1 patent drawing
  • US20240420765A1 patent drawing
  • US20240420765A1 patent drawing

AI summary

A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.