Semiconductor Storage Circuit Scan Test Data Inhibition
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Solution Overview
Problem
In semiconductor apparatuses, executing a scan test can result in data overwrite in storage circuits accessed by the test target processing circuit, leading to performance degradation and cache errors, especially in cache memory scenarios.
Innovation Solution
A semiconductor apparatus design that inhibits data writing from the processing circuit to the storage circuit during a scan test, using mechanisms like reset mask circuits and initialization mask circuits to maintain data integrity and prevent unintended data changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a scan test is executed on a processing circuit that accesses a storage circuit, then the processing circuit can be tested for faults, but data stored in the storage circuit is overwritten
Solution Approach 1:
The patent segments the storage circuit into test mode and normal operation mode. During scan test execution, the storage circuit is isolated from normal write operations by the processing circuit, allowing the test to access storage locations without permitting other write operations that would overwrite test data or valid stored data.
Solution Approach 2:
The patent implements preliminary actions by setting up control logic before the scan test begins. The control circuit is configured to detect test mode signals and preemptively prevent write operations to the storage circuit during the test period, ensuring data protection is in place before any potential overwrite can occur.
2Productivity
If the processing circuit is reset after a scan test to resume operation, then normal processing can continue, but data stored in the storage circuit is initialized
Solution Approach 1:
The patent implements dynamic control of the storage circuit's write enable signal based on the operational state. The control circuit dynamically adjusts the write enable signal to be asserted during normal operation but deasserted during scan test execution and reset periods, allowing the system to adapt its behavior to current operational requirements and prevent unintended data initialization.
Solution Approach 2:
The patent introduces a control circuit as an intermediary between the processing circuit and the storage circuit. This intermediary monitors the operational state and controls the write enable signal, acting as a mediator that prevents direct write access to storage during test and reset operations while allowing normal writes during regular processing.
3Reliability
If a scan test is executed on a processing circuit, then the circuit can be diagnosed, but unintended writing of data occurs from the processing circuit to the storage circuit
Solution Approach 1:
The patent applies preliminary anti-action by implementing control logic that anticipates and prevents unintended write operations during scan test execution. The control circuit detects when a scan test is in progress and preemptively blocks write signals from the processing circuit to the storage circuit, counteracting the potential harmful effect before it can occur.
Data Source
AI summary
A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.