Semiconductor Storage Device Select Gate Voltage Control
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Solution Overview
Problem
Conventional semiconductor storage devices have limitations in processing capacity, particularly in erase operations, where the length of the semiconductor layer in memory pillars can lead to insufficient hole supply to memory cell transistors, resulting in longer erase times and potential over-erasing, which increases the processing time for both erase and write operations.
Innovation Solution
The semiconductor storage device incorporates select transistors for generating gate-induced drain leakage (GIDL) current and allows independent voltage application to select gate lines, enabling efficient hole supply to memory cell transistors from both the bit line and source line sides, facilitating both block and sub-block erase operations, and preventing over-erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor layer length in memory pillars is increased, then the memory cell capacity is improved, but the hole supply to memory cell transistors becomes insufficient, resulting in longer erase times
Solution Approach 1:
The memory pillar is segmented into multiple sections with select transistors (STT1, ST1, ST2, STB2, STB1) positioned at different heights along the semiconductor layer. This segmentation allows independent control of different memory cell regions, enabling holes to be supplied from multiple locations (bit line side and source line side) simultaneously, thereby resolving the hole supply insufficiency issue in long semiconductor layers while maintaining high memory capacity
Solution Approach 2:
Select transistors serve as intermediary control elements between the bit line/source line and the memory cell transistors. By applying specific voltages to the select gate lines (SGDT, SGD, SGS, SGSB) connected to these select transistors, the patent enables controlled hole injection into memory cell transistors at different positions along the semiconductor layer, ensuring sufficient hole supply even when the semiconductor layer is long
2Volume of moving object
If the semiconductor layer length in memory pillars is increased, then the memory cell capacity is improved, but the processing capacity for write operations decreases due to potential over-erasing
Solution Approach 1:
Different select gate lines (SGDT, SGD, SGS, SGSB) are assigned different voltage levels during erase operations to create local quality differences in hole injection. This allows precise control over which memory cell regions receive holes and to what extent, preventing over-erasing in certain regions while ensuring adequate erasing in others, thereby maintaining high processing capacity alongside increased memory capacity
Solution Approach 2:
The patent employs multiple voltage parameters (Vera for bit line/source line, Verasgdt for SGDT, Verasgsb for SGSB, Verasgd for SGD, Verasgs for SGS) to control the erase operation. By independently adjusting these voltage parameters, the system can optimize the erase process for long semiconductor layers, preventing over-erasing while maintaining high processing capacity and utilizing the full memory capacity
3Productivity
If independent voltage application to select gate lines is implemented, then hole supply efficiency is improved, but the device complexity increases
Solution Approach 1:
The select transistors and their associated select gate lines serve multiple functions: they control hole injection during erase operations, enable sub-block erase functionality, and provide selective access to different memory cell regions during read/write operations. This multi-functionality justifies the increased device complexity by delivering significant improvements in hole supply efficiency and overall processing capacity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances processing capacity by ensuring sufficient hole supply to all memory cell transistors, reducing erase and write operation times, and minimizing over-erasing, thereby improving overall device performance.
Implementation Method 1
select transistors for generating gate-induced drain leakage (GIDL) current
Data Source
AI summary
A semiconductor storage device includes a memory string and a row decoder configured to apply voltages to first to fourth select gate lines and first and second word lines connected to the memory string. A sequencer has first mode for erasing the entire memory string and a second mode for erasing just a portion of the memory string. In the first mode, a first voltage is applied to the bit line and the source line, a second voltage lower than the first voltage is applied to the first select gate line, a third voltage is applied to the second select gate line, a fourth voltage is applied to the third select gate line, a fifth voltage lower than the first voltage is applied to the fourth select gate line, and a sixth voltage lower than the first to fifth voltages is applied to the first and second word lines.