Semiconductor Storage Device Signal Segmentation for Chip Selection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing memory systems require a dedicated memory controller and additional signal lines to manage multiple memory chips, limiting their scalability and increasing manufacturing costs.

Innovation Solution

A semiconductor storage device design that uses a general-purpose memory controller with a selection unit and a switch unit, dividing the chip selection signal into two signals to enable the selection of multiple memory chips without adding additional signal lines, allowing for increased chip count and reduced manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a dedicated memory controller with additional signal lines is used to manage multiple memory chips, then the number of selectable chips increases, but the manufacturing cost increases and general purpose components cannot be used

Engineering Contradiction:
Improvenumber of selectable chipsVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The chip selection signal is segmented into two separate signals: a first signal transmitted directly from the memory controller to the selection unit, and a second signal transmitted from the memory controller to the switch unit. This segmentation allows the system to control multiple memory chips using the same signal lines, eliminating the need for additional dedicated signal lines and enabling the use of general purpose memory controllers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A switch unit is introduced as an intermediary component between the memory controller and the selection unit. The switch unit receives the second signal from the memory controller and controls the connection between the selection unit and multiple memory chips. This intermediary enables signal reuse and allows a general purpose memory controller to manage more chips than the number of physical signal lines would normally permit.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If additional signal lines are added to the memory controller to select more memory chips, then the number of selectable chips increases, but the device complexity increases

Engineering Contradiction:
Improvenumber of selectable chipsVSAvoidsignal line complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The chip selection functionality is segmented across two signal paths: one path carries the first signal from the memory controller to the selection unit, and the other path carries the second signal from the memory controller to the switch unit. This segmentation allows the system to logically extend chip selection capability without physically adding more signal lines to the memory controller, thereby maintaining signal line simplicity while increasing adaptability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system adds a temporal or control dimension to chip selection by introducing the switch unit that responds to the second signal. Instead of adding more spatial dimensions (signal lines), the invention uses a control dimension where the switch unit dynamically configures connections based on the second signal, enabling more chips to be selected through time-multiplexed or dynamically routed signal usage.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10614014B2Semiconductor storage device having a memory controller, a selection unit and a switch unit connected to each other
Publication Date: 2020.04.07 HITACHI VANTARA LTD
  • US10614014B2 patent drawing
  • US10614014B2 patent drawing
  • US10614014B2 patent drawing

AI summary

To increase the number of selectable chips without adding a signal line to a general purpose memory controller. A semiconductor storage device includes a memory controller, a plurality of memory chips, a selection unit which is connected to the memory controller and is connected with the plurality of memory chips to be able to select any one of the plurality of memory chips, and a switch unit which is connected to the memory controller and the selection unit. The memory controller and the selection unit are connected by a signal line for transmitting a first signal outputted from the memory controller and configured to select the memory chips. The memory controller and the switch unit are connected by a signal line for transmitting a second signal outputted from the memory controller and configured to select the memory chips.