Semiconductor Storage Device Source Line Potential Control
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in reducing current leakage in standby mode while maintaining proper data retention and minimizing circuit area, as previous configurations either require large areas for independent transistors or struggle with proper sizing of single transistors to control source line potentials effectively.
Innovation Solution
A semiconductor storage device design featuring a memory array with multiple memory cells and a control circuit that includes two switching transistors and a source line potential control circuit, where the first switching transistor is non-conductive and the second switching transistor is diode-coupled in standby mode, allowing for efficient adjustment of source line potential and reduced current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single diode-coupled transistor is used to control source line potential, then area is reduced, but the transistor cannot be properly sized to bring source lines down to ground potential in normal mode
Solution Approach 1:
The control function is segmented into two separate transistors: a first diode-coupled transistor for raising source line potential in standby mode, and a second switching transistor for bringing source lines down to ground potential in normal mode. This segmentation allows each transistor to be optimally sized for its specific function, resolving the sizing conflict that prevented proper ground potential control when using a single transistor.
2Reliability
If independent transistors are provided for raising and controlling source lines, then proper potential control is achieved, but area increases
Solution Approach 1:
The first diode-coupled transistor and the second switching transistor are merged into a unified control structure where they share common connections to the source line and are coordinated by a single control signal. This merging approach achieves proper potential control for both standby and normal modes while minimizing the total area required compared to fully independent transistor implementations.
3Loss of energy
If transistor size is reduced to reduce standby current, then area is reduced, but the transistor cannot bring source lines down to ground potential in normal mode
Solution Approach 1:
The control function is segmented into two separate transistors: a first diode-coupled transistor for raising source line potential in standby mode, and a second switching transistor for bringing source lines down to ground potential in normal mode. This segmentation allows each transistor to be optimally sized for its specific function, resolving the sizing conflict that prevented proper ground potential control when using a single transistor.
4Reliability
If transistor size is increased to bring source lines to ground potential, then proper potential control is achieved, but standby current increases
Solution Approach 1:
The control circuit dynamically switches between two transistor configurations based on operational mode: in standby mode, the first diode-coupled transistor is activated to raise source line potential and reduce leakage current, while in normal mode, the second switching transistor is activated to bring source lines to ground potential for proper data retention. This dynamic switching allows optimal performance for each mode without compromising the other.
Data Source
AI summary
A semiconductor storage device includes, a memory array, a plurality of memory cells provided in rows and columns, and a control circuit for controlling the memory array, each of the memory cells being a static-type memory cell comprising driving transistors, transfer transistors, and load elements.