Semiconductor Storage Device Via Reduction
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Solution Overview
Problem
Current semiconductor storage devices, particularly NAND-type flash memories with three-dimensionally stacked memory cells, face challenges in integrating memory cell transistors efficiently, leading to limitations in integration characteristics and increased risk of manufacturing errors due to high density and complex interconnectivity.
Innovation Solution
The semiconductor storage device employs a stacked body with alternately arranged conductive and insulating layers, columnar bodies with semiconductor and charge storage films, and a specific configuration of bit lines and contacts to enhance integration and reduce the number of vias, thereby improving memory cell transistor integration and reducing the risk of short-circuiting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in three dimensions to increase storage capacity, then storage density is improved, but manufacturing complexity and error risk increase
Solution Approach 1:
The memory device is segmented into multiple string units, each with independent bit lines and word lines. This segmentation allows parallel processing and reduces the complexity of controlling individual memory cells, as entire strings can be addressed collectively rather than cell-by-cell.
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional stacked architecture. Memory cell strings are vertically stacked above the substrate, with conductive layers and insulating layers forming multiple levels. This dimensional change increases storage capacity without proportionally increasing manufacturing complexity.
2Adaptability or versatility
If the number of vias is increased to connect more memory cells, then connectivity is improved, but the risk of short-circuiting increases
Solution Approach 1:
Multiple memory cell strings share common source lines and drain lines. Instead of providing dedicated interconnects for each individual memory cell, the patent merges interconnect resources at the string level, reducing the total number of vias required while maintaining adequate connectivity across all memory cells.
Solution Approach 2:
The bit lines and word lines serve multiple functions: they address and control multiple memory cell strings simultaneously, enable read and write operations, and provide signal routing across different vertical levels. This multi-functionality reduces the need for specialized interconnect structures.
Data Source
AI summary
A semiconductor storage device according to an embodiment includes a stacked body in which a conductive layer and an insulating layer are stacked alternately in a first direction, a plurality of columnar bodies that extend in the first direction inside the stacked body and each include a semiconductor body, a plurality of charge storage films that are disposed between at least one of a plurality of the conductive layers and each of a plurality of the semiconductor bodies, a plurality of bit lines that extend above the stacked body in a second direction intersecting the first direction, an interlayer insulating layer that is between the stacked body and the bit lines, and contacts each of which penetrates the interlayer insulating layer and is electrically connected to one of the plurality of bit lines, in which the contacts have a first contact that is connected to one of the columnar bodies and a second contact that is connected to a plurality of the columnar bodies.