Semiconductor Storage Voltage Generating Circuit Area Reduction
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Solution Overview
Problem
The challenge in semiconductor storage devices is to minimize the area of the voltage generating circuit while maintaining effective voltage generation for erasing data, as existing solutions face limitations in reducing resistance element size without increasing current consumption or compromising resistance value.
Innovation Solution
The semiconductor storage device employs a voltage generating circuit with a transistor, resistance elements, and a comparator, featuring a wiring structure with resistance wiring portions of the same fine line width as other semiconductor components, allowing for high resistance values with minimal area and reduced current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the resistance element size is reduced to minimize circuit area, then the area of the voltage generating circuit is reduced, but the current consumption increases
Solution Approach 1:
The patent applies different line widths to different portions of the resistance element wiring. Specifically, the resistance wiring portions have a first line width while the connection wirings have a second line width that is larger than the first. This local differentiation allows the resistance-generating portions to occupy minimal area while the connection portions use larger widths to maintain appropriate resistance values and current characteristics, thereby resolving the contradiction between minimizing circuit area and controlling current consumption.
2Area of stationary object
If the resistance element size is reduced to minimize circuit area, then the area of the voltage generating circuit is reduced, but the resistance value decreases
Solution Approach 1:
The patent differentiates the line widths of different wiring portions within the resistance element structure. The resistance wiring portions use a first line width optimized for generating the required resistance value, while the connection wirings use a second, larger line width for reliable electrical connection. This local quality differentiation ensures that the resistance value is maintained at appropriate levels even when the overall element size is reduced, thereby resolving the contradiction between minimizing area and maintaining resistance value.
Solution Approach 2:
The patent utilizes multi-layer wiring structures to implement the resistance element. By arranging resistance wiring portions and connection wirings in different layers and utilizing vertical stacking, the patent achieves compact area occupation while maintaining sufficient resistance values through optimized current paths. This dimensional approach allows the resistance element to be small in planar area while preserving its electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a high-quality power supply generating circuit with reduced circuit area and minimal current consumption, effectively addressing the need for efficient voltage generation in semiconductor storage devices.
Implementation Method 1
The resistance wiring portions (105) have a line width that is equal to a finest line width among wirings formed in the memory region (11). The first resistance element (22) and the second resistance element (23) each have the wiring structure (31) for resistance.
Data Source
AI summary
A semiconductor storage device has a nonvolatile storage region, a voltage generating circuit that generates an operational voltage for the storage region, and a control circuit that sends the voltage generated by the voltage generating circuit to the storage region. The voltage generating circuit has a transistor, a first resistance element, a second resistance element, and a comparator. The first resistance element and the second resistance element have wiring structure for resistance. The resistance wiring in the wiring structure has the same line width as the finest line width in the wiring formed in the storage region.