Semiconductor Storage Device Voltage Control for Laminated Memory Arrays
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Solution Overview
Problem
In three-dimensional memory cell arrays, reverse-biased voltages applied to non-selected memory cells lead to increased leak currents, which can result in higher power consumption and potential erroneous data writing, especially when multiple memory cell arrays are laminated and one is selected, causing reverse-biased voltage to be applied to many non-selected cells.
Innovation Solution
A semiconductor storage device with a control circuit that selectively applies different potentials to shared first and second wirings of adjacent memory cell arrays, minimizing reverse-biased voltages on non-selected memory cells by setting all first and second wirings of non-selected memory cell arrays to specific potentials, thereby reducing leak currents and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If reverse-biased voltage is applied to non-selected memory cells in laminated three-dimensional memory cell arrays, then memory cell arrays can be laminated to increase storage capacity, but leak current increases and power consumption increases
Solution Approach 1:
The patent divides the memory cell arrays into selected and non-selected groups, and further segments non-selected arrays into adjacent and distant categories. Different voltage potentials are applied to different segments: selected arrays receive voltages for normal operation, adjacent non-selected arrays receive first standard potential on first wirings and second standard potential on second wirings to minimize reverse bias, and distant non-selected arrays receive first potential on all wirings. This segmentation allows the system to maintain high storage capacity through lamination while reducing leak current in non-selected cells by applying appropriate potentials to different segments.
Solution Approach 2:
The patent applies different voltage potentials to different spatial locations and memory cell states. Specifically: selected memory cells receive voltages for read/write operations; adjacent non-selected memory cells sharing wirings with selected cells receive first standard potential on first wirings and second standard potential on second wirings to minimize reverse-biased voltage; and distant non-selected memory cells receive first potential on all wirings. This local differentiation of voltage quality reduces leak current in non-selected cells while maintaining proper operation of selected cells, thereby reducing power consumption without sacrificing storage capacity.
2Quantity of substance
If reverse-biased voltage is applied to non-selected memory cells, then memory cell arrays can be laminated to increase storage capacity, but power consumption increases
Solution Approach 1:
The patent segments non-selected memory cell arrays into adjacent and distant categories and applies different voltage potentials to each segment. Adjacent non-selected arrays (sharing wirings with selected cells) receive first standard potential on first wirings and second standard potential on second wirings, while distant non-selected arrays receive first potential on all wirings. This segmentation strategy minimizes reverse-biased voltage in non-selected cells, thereby reducing leak current and power consumption while preserving the high storage capacity enabled by lamination.
Solution Approach 2:
The patent implements local quality control by applying different voltage potentials to different spatial locations and operational states. Selected cells receive operational voltages, adjacent non-selected cells receive potentials that minimize reverse bias (first standard potential on first wirings, second standard potential on second wirings), and distant non-selected cells receive first potential on all wirings. This localized voltage optimization reduces overall power consumption by minimizing leak current in non-selected cells while maintaining the laminated structure for high storage capacity.
3Quantity of substance
If reverse-biased voltage is applied to non-selected memory cells, then memory cell arrays can be laminated to increase storage capacity, but erroneous data writing may occur
Solution Approach 1:
The patent segments memory cell arrays into selected and non-selected groups, with non-selected further divided into adjacent and distant categories. Selected cells receive voltages for reliable read/write operations. Adjacent non-selected cells (sharing wirings with selected cells) receive first standard potential on first wirings and second standard potential on second wirings, which minimizes reverse-biased voltage and prevents erroneous data writing. Distant non-selected cells receive first potential on all wirings. This segmentation ensures that non-selected cells do not experience harmful reverse bias that could cause data corruption, while the laminated structure maintains high storage capacity.
Solution Approach 2:
The patent applies different voltage potentials to different local regions and operational states to ensure data integrity. Selected memory cells receive appropriate voltages for reliable operations. Adjacent non-selected memory cells receive first standard potential on first wirings and second standard potential on second wirings, creating a local voltage environment that minimizes reverse bias and prevents erroneous writing. Distant non-selected cells receive first potential on all wirings. This local quality control mechanism protects against data corruption in non-selected cells while preserving the high storage capacity of the laminated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes leak currents and power consumption by optimizing voltage application across non-selected memory cell arrays, ensuring accurate data writing and reducing operational inefficiencies in three-dimensional memory cell arrays.
Implementation Method 1
The Resistive RAM store resistance states in a nonvolatile manner with transition metal oxide being used as a recording layer.
Implementation Method 2
The control circuit is operative to provide, in a first memory cell array selected from among the plurality of the memory cell arrays, a first potential to a selected first wiring, a first standard potential that is lower than the first potential to a non-selected first wiring, a second potential that is lower than the first potential to a selected second wiring, and a second standard potential that is higher than the second potential to a non-selected second wiring.
Data Source
AI summary
Plural memory cell arrays laminated on the semiconductor substrate each includes a plurality of first wirings and second wirings formed to intersect with each other. The control circuit provides, in a non-selected second memory cell array that shares the first wiring with a selected first memory cell array, and a non-selected third memory cell array located more distant from the first memory cell array than the second memory cell array, the first potential to all of the first wirings and all of the second wirings. It also provides, in a non-selected fourth memory cell array that shares the second wiring with the first memory cell array and a non-selected fifth memory cell array located more distant from the first memory cell array than the fourth memory cell array, the second potential to all of the first wirings and all of the second wirings.