Semiconductor Storage Device Voltage Slope Control for Snapback Prevention
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in reading and writing data without applying stress to memory cells, leading to reliability issues due to high voltage requirements and potential data destruction during read operations.
Innovation Solution
A semiconductor storage device configuration that applies a voltage with a first slope followed by a second slope, which is smaller, to memory cells, allowing for reliable data writing and reading by preventing snapback and reducing stress on the memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high voltage is applied to read data from the memory cell, then the read operation can be performed, but the memory cell may be destroyed due to snapback phenomenon
Solution Approach 1:
The bit line voltage is lowered before the word line voltage is raised during the read operation. This preliminary action prepares the voltage conditions to prevent snapback from occurring, allowing safe reading of data from the memory cell without destruction
Solution Approach 2:
The patent dynamically adjusts the voltage application sequence and timing based on the operational phase (read vs write). During read operations, voltages are applied in a controlled sequence that adapts to prevent snapback, while write operations use different voltage patterns to ensure proper data storage
2Reliability
If a high voltage is applied to write data to the memory cell, then the write operation can be performed, but stress is applied to the memory cell structure
Solution Approach 1:
The write operation uses periodic pulsed voltages with specific timing characteristics. By controlling the duration and timing of voltage pulses applied to word lines and bit lines, the patent achieves reliable data writing while limiting the total stress exposure to the memory cell structure
Solution Approach 2:
The patent changes voltage parameters (magnitude, timing, duration) based on the operational requirements. Different voltage levels and pulse widths are used for write operations compared to read operations, optimizing both write success and stress minimization through parameter adjustment
3Reliability
If conventional voltage application method is used, then simple control is achieved, but read disturb occurs and data may be incorrectly modified
Solution Approach 1:
Before performing a read operation, the patent applies preliminary voltage conditioning to adjacent memory cells and control lines. This preliminary action prevents voltage leakage or unintended effects on neighboring cells, eliminating read disturb while maintaining accurate data retrieval
Solution Approach 2:
The patent introduces intermediate control signals and voltage regulation mechanisms that mediate between the read operation and the memory cell array. These intermediary elements control voltage distribution to ensure only the targeted cell is accessed while protecting adjacent cells from disturbance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of semiconductor storage devices by reducing stress on memory cells during operations, improving data integrity and reducing the risk of data destruction during read and write processes.
Implementation Method 1
a memory cell having a first end connected to a first wiring and a second end connected to a second wiring, and a control circuit configured to apply a voltage that increases with a first slope and then with a second slope that is smaller than the first slope, to the memory cell using the first wiring and the second wiring
Data Source
AI summary
A semiconductor storage device includes a first wiring, a second wiring, a memory cell including a first element configured to store data and a second element connected to the first element, the memory cell having a first end connected to the first wiring and a second end connected to the second wiring, and a control circuit configured to apply a voltage that increase with a first slope and then with a second slope that is smaller than the first slope, to the memory cell using the first wiring and the second wiring.