Semiconductor Storage Device Program Operation Voltage Timing
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Solution Overview
Problem
Current semiconductor storage devices face challenges in efficiently controlling the threshold voltage distribution of memory cells, leading to increased error bits and potential circuit area expansion due to the need for additional transistors in sense amplifiers.
Innovation Solution
The semiconductor storage device employs a program operation that sequentially switches the channel-gate voltage of memory cells at specific timings, controlling the electron accumulation in the charge storage film in multiple stages, without increasing the number of transistors in the sense amplifier, by adjusting voltages applied to bit lines and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional transistors are added to the sense amplifier to control threshold voltage distribution, then the control precision is improved, but the circuit area increases
Solution Approach 1:
The patent changes the voltage parameters applied to bit lines and word lines during the program operation. By applying different voltage levels (first voltage to first bit line, second voltage to second bit line, third voltage to word line) at different timings, the patent controls the threshold voltage distribution of memory cells without adding transistors to the sense amplifier, thus improving control precision while maintaining compact circuit area.
Solution Approach 2:
The patent employs periodic voltage switching actions during the program operation. Voltages are applied and switched at specific timings (first timing for first bit line, second timing for second bit line, third timing for word line) to control electron accumulation in stages, achieving precise threshold voltage control through time-dependent voltage modulation rather than through additional circuit components.
2Manufacturing precision
If voltage switching timing is optimized to control electron accumulation stages, then the threshold voltage distribution is narrowed, but the program operation complexity increases
Solution Approach 1:
The patent segments the program operation into multiple timing stages with distinct voltage applications. The first voltage is applied at a first timing, the second voltage at a second timing, and the third voltage at a third timing. This segmentation allows controlled electron accumulation in stages, narrowing the threshold voltage distribution while managing complexity through structured timing control.
Solution Approach 2:
The patent applies preliminary voltage actions to bit lines and word lines before completing the program operation. By raising voltages at predetermined timings during the program sequence, the patent prepares the electrical conditions necessary for controlled electron accumulation, achieving precise threshold voltage control through pre-planned voltage scheduling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach narrows the threshold voltage distribution, reduces error bits, and maintains a compact circuit design by controlling electron accumulation stages without adding transistors to the sense amplifier.
Implementation Method 1
raising a first voltage applied to the first bit line at a first timing, raising a second voltage applied to the word line at a second timing after the first timing, raising a third voltage applied to the second bit line at a third timing after the second timing
Data Source
AI summary
A semiconductor storage device includes first, second, and third transistors, first, second, and third bit lines connected to the first, second, and third transistors, a word line connected to the first, second, and third transistors, and a control circuit configured to perform a program operation for writing data to the second and third transistors, including raising a first voltage applied to the first bit line at a first timing, raising a second voltage applied to the word line at a second timing, raising a third voltage applied to the second bit line at a third timing, raising a fourth voltage applied to the third bit line at a fourth timing, and lowering the first voltage at a fifth timing. The first voltage is raised to a first predetermined voltage, and each of the third and fourth voltages is raised to a second predetermined voltage smaller than the first predetermined voltage.