Semiconductor Storage Device Wiring Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor storage devices face challenges in reducing the chip area and current density of signal lines due to the presence of thick power lines and signal wirings in the CMOS chip, which restricts layout and increases chip size.
Innovation Solution
The semiconductor storage device addresses this by bonding a CMOS chip with a memory cell array chip, where trunk power lines and signal lines are routed in the memory cell array chip, allowing the CMOS chip to omit these wiring regions and reduce current density through a flip-chip bonding method with pad electrodes connecting power and signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick power lines and signal wirings are provided in the CMOS chip, then power supply and signal transmission are ensured, but chip area increases and layout flexibility decreases
Solution Approach 1:
The patent divides the wiring function into two parts: the CMOS chip retains only essential local wirings, while the memory cell array chip provides additional power lines and signal wirings. This segmentation allows each chip to have optimized wiring layouts without being constrained by the other's wiring requirements, reducing the total chip area while maintaining reliable power supply and signal transmission.
Solution Approach 2:
The patent utilizes the third dimension (vertical stacking) by bonding the memory cell array chip to the CMOS chip. This allows wirings to be distributed across multiple layers/chips rather than confined to a single planar layer, enabling better wiring density and reduced chip area while maintaining all necessary electrical connections.
2Power
If thick power lines are provided in the CMOS chip, then current capacity is sufficient, but current density increases and chip size increases
Solution Approach 1:
The patent segments the power delivery function between two chips: the CMOS chip provides local power distribution, while the memory cell array chip provides additional power lines with sufficient current capacity. This division allows the CMOS chip to use thinner power lines (reducing its area) while the overall system maintains adequate current capacity through the combined wiring of both chips.
3Ease of operation
If signal wirings are routed in the CMOS chip, then signal transmission is achieved, but wiring region increases and layout efficiency decreases
Solution Approach 1:
The patent segments the signal transmission function: the CMOS chip handles local signal routing, while the memory cell array chip provides additional signal wiring pathways. This segmentation reduces the wiring region in the CMOS chip, improving layout efficiency, while signal transmission remains achieved through the combined wiring infrastructure of both chips.
4Area of stationary object
If chip bonding is used to separate control circuit and memory cell array, then chip occupancy is reduced, but wiring complexity between chips increases
Solution Approach 1:
The patent makes the memory cell array chip multi-functional: it serves both as the memory storage array and as a wiring carrier for power lines and signal connections to the CMOS chip. This universality reduces wiring complexity because the memory chip's existing wiring infrastructure is utilized for multiple purposes, rather than requiring separate dedicated wiring layers.
Data Source
AI summary
A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.