Semiconductor Storage Device Write Operation Interference Management
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Solution Overview
Problem
The existing semiconductor storage devices face challenges in shortening the time required for write operations due to interference effects from adjacent memory cells, which affect the threshold voltage distribution and accuracy of data storage.
Innovation Solution
The implementation of a semiconductor storage device configuration with independently controlled first and second word lines, where memory pillars are arranged in intersecting directions, allowing for a controlled write operation to the second memory cell after the first memory cell, optimizing the write operation by managing interference and threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write operation is performed to adjacent memory cells simultaneously to shorten write time, then productivity is improved, but threshold voltage distribution becomes wider due to interference effects
Solution Approach 1:
The write operation is divided into multiple stages with different voltage levels. A first write operation applies a first program voltage to a first memory cell, followed by a second write operation that applies a second program voltage (higher than the first) to a second memory cell. This segmentation allows controlled interference management while maintaining write speed.
Solution Approach 2:
The first write operation to the first memory cell is performed before the second write operation to the second memory cell. This preliminary action establishes a baseline threshold voltage distribution that can tolerate controlled interference from subsequent operations, enabling faster overall write performance.
2Productivity
If program voltage is increased to improve write speed, then productivity is improved, but interference effects on adjacent memory cells increase
Solution Approach 1:
The write operation uses periodic voltage pulses with different magnitudes. A first program voltage is applied in an initial period, followed by a second program voltage with higher magnitude in a subsequent period. This periodic action with varying voltage levels enables controlled writing while managing interference effects through the timing and magnitude variations.
Solution Approach 2:
The program voltage parameter is changed between different write operations. The second program voltage is set higher than the first program voltage to achieve faster writing to the second memory cell, while the sequential timing and voltage level changes are controlled to manage interference effects on adjacent cells.
Data Source
AI summary
A semiconductor storage device includes a first word line, a second word line provided in the same layer with the first word line and configured to be controlled independently from the first word line, a plurality of memory pillars between the first word line and the second word line, each of the plurality of memory pillars including a first memory cell facing to the first word line and a second memory cell facing to the second word line, the plurality of memory pillars being arranged in a first direction and a second direction intersecting to the first direction and a control circuit. The control circuit is configured to perform a write operation to the second memory cell included in the plurality of memory pillars after performing a write operation to the first memory cell included in each of the plurality of memory pillars.