Strain Engineering in Semiconductor Layers for NMOS PMOS Mobility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in fabricating n-type and p-type metal-oxide-semiconductor field effect transistors with optimal strain states within a common layer on a semiconductor substrate, as existing methods do not effectively enhance both electron and hole mobility simultaneously.
Innovation Solution
A method involving a semiconductor-on-insulator substrate with a stressor layer and dielectric layer, where ions are implanted to alter strain states in specific regions, allowing for the formation of compressively strained and tensiley strained surface semiconductor layers, enabling the fabrication of NMOS and PMOS transistors with improved mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common layer structure is used for both NMOS and PMOS transistors, then device integration is simplified, but it becomes difficult to provide optimal strain states for both electron and hole mobility enhancement simultaneously
Solution Approach 1:
The patent applies local quality by introducing region-specific stressor layers with different materials and strain characteristics within the common layer structure. First and second stressor layers are selectively positioned beneath NMOS and PMOS channels respectively, providing locally optimized tensile or compressive strain states tailored to each transistor type's mobility requirements while maintaining overall structural integration
Solution Approach 2:
The patent segments the stressor layer into distinct first and second stressor layers with different functional characteristics. This segmentation allows independent optimization of strain states for different transistor regions, enabling simultaneous enhancement of electron mobility in NMOS and hole mobility in PMOS within a unified layer architecture
2Reliability
If different strain states are applied to enhance electron mobility in NMOS and hole mobility in PMOS, then device performance is improved, but the fabrication process complexity increases
Solution Approach 1:
The patent merges multiple strain enhancement functions into a single integrated layer structure comprising substrate, surface semiconductor layer, and multiple stressor layers. This consolidation achieves simultaneous mobility enhancement for both NMOS and PMOS transistors through a unified fabrication process, avoiding the need for separate strain engineering processes while maintaining distinct strain states in different regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous enhancement of electron and hole mobility in NMOS and PMOS transistors, respectively, by altering strain states in specific regions, leading to improved device performance.
Implementation Method 1
Ions are implanted into or through at least a first region of the stressor layer without implanting ions into or through at least a second region of the stressor layer
Data Source
Figure 1~3
Figure 4~6
Figure 7~9
AI summary
Methods of fabricating a semiconductor structure include providing a semiconductor-on- insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.