Strain Control in Semiconductor Source and Drain Regions
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Solution Overview
Problem
Current methods for strain control in transistor channel regions face challenges in achieving high driving current while minimizing defects and maintaining strain concentration, particularly due to low solid solubility of strain atoms in silicon crystals and the risk of surface defects from high-concentration carbon atom implantation.
Innovation Solution
A method involving multiple strain atom implantations with different energies and dosages, followed by a solid-phase epitaxy annealing process, to form a semiconductor compound solid-phase epitaxy layer, ensuring uniform strain distribution and reducing surface defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-concentration carbon atoms are implanted at one time, then the required surface concentration of strain atoms is achieved, but defects form on the surface of source and drain regions causing leakage
Solution Approach 1:
The patent divides the single high-concentration implantation process into multiple sequential implantation steps. Each step implants carbon atoms at a controlled concentration level, allowing the crystal structure to gradually accommodate the strain atoms without forming surface defects. This segmented approach maintains the cumulative effect of high surface concentration while avoiding the harmful effects of single-step oversaturation.
2Quantity of substance
If the solid solubility of strain atoms in silicon crystals is low, then the concentration of semiconductor compound solid-phase epitaxy layer is low, but multiple implantation steps are required to achieve high concentration
Solution Approach 1:
The patent implements a continuous multi-step implantation process where each step builds upon the previous one. The carbon atom implantation is performed in sequential stages, with each stage contributing to the cumulative concentration in the solid-phase epitaxy layer. This continuous action over multiple steps overcomes the low solid solubility limitation by gradually saturating the crystal structure.
3Speed
If device dimensions are reduced to attain higher operating speed and lower power consumption, then operating speed increases, but device miniaturization reaches its limit and driving current decreases
Solution Approach 1:
The patent changes the physical and chemical parameters of the source and drain regions by forming semiconductor compound solid-phase epitaxy layers with different compositions (SiC, SiGe, SiBC). These parameter changes in material composition create strain in the channel region, which enhances carrier mobility and maintains driving current even as device dimensions are reduced for higher operating speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the driving current and reliability of semiconductor devices by maintaining high strain levels while minimizing surface defects and eliminating the need for additional annealing processes, providing a flexible and competitive manufacturing method.
Implementation Method 1
High-concentration carbon atoms are implanted into source and drain regions
Implementation Method 2
SiC is formed therein by a solid-phase epitaxy annealing process
Implementation Method 3
a solid-phase epitaxy annealing process is performed so that each strained region forms a semiconductor compound solid-phase epitaxy layer
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. A gate structure is formed on a substrate. A first dopant implantation and a first strain atom implantation are performed. Thereafter, spacers are formed on sidewalls of the gate structure. A second dopant implantation and a second strain atom implantation are performed. A solid-phase epitaxy annealing process is performed to form source and drain regions made of a semiconductor compound solid-phase epitaxial layer beside the gate structure.