Selective Strain Alteration in Semiconductor Transistor Channels
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Solution Overview
Problem
Current semiconductor technologies face challenges in fabricating n-type and p-type metal-oxide-semiconductor field effect transistors with different stress states in a common layer on a semiconductor substrate, as existing methods struggle to efficiently alter and maintain distinct strain states for optimal conductivity in finFET structures.
Innovation Solution
A method involving a multi-layer substrate with a buried oxide layer and a strained semiconductor layer, where ions are implanted into specific regions to convert crystalline material to amorphous and then recrystallize it, diffusing elements to alter the strain state, allowing for the formation of n-type and p-type transistor channel structures with differing crystallographic strains in a common plane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single strained semiconductor layer is used for both n-type and p-type transistors, then fabrication is simplified, but both transistor types cannot achieve optimal conductivity simultaneously
Solution Approach 1:
The patent applies local quality by creating different strain states in different regions of the semiconductor layer. Specifically, a first region is maintained in a first strain state (e.g., tensile strain) for n-type transistors, while a second region is converted to a second strain state (e.g., compressive strain) for p-type transistors. This is achieved through selective ion implantation and recrystallization processes that modify the crystal structure locally without affecting the entire layer, allowing each transistor type to operate at optimal conductivity.
2Reliability
If different strained semiconductor layers are used for n-type and p-type transistors, then optimal conductivity for each type is achieved, but fabrication complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor layer into distinct regions (first region and second region) that undergo different processing treatments. The selective ion implantation targets specific geographic areas of the layer, creating segmented zones with different strain states. This approach avoids the need for completely separate semiconductor layers while still achieving the functional differentiation needed for optimal n-type and p-type transistor performance.
Solution Approach 2:
The patent applies parameter changes by modifying the strain state parameter in different regions of the same semiconductor layer. Through controlled ion implantation and recrystallization, the crystal structure parameters (strain state) are changed locally from a first strain state to a second strain state in the second region, while the first region maintains its original strain state. This allows a single layer to provide the different material properties needed for both n-type and p-type transistors.
3Stability of the object's composition
If ion implantation is performed on the entire semiconductor layer, then uniform doping is achieved, but selective strain state modification cannot be implemented
Solution Approach 1:
The patent applies the taking out principle by selectively removing the ion implantation treatment from certain regions. A mask layer is used to prevent ion implantation in the first region while allowing it in the second region. This selective extraction of the implantation process enables different strain states to be created in different regions, achieving both uniform doping where applied and strain state differentiation where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of n-type and p-type transistors with improved electron and hole mobility by selectively altering strain states, enhancing the performance and reducing threshold voltage of finFET transistors, while allowing for co-planar fabrication in the same device.
Implementation Method 1
implanting ions into a second region of the strained semiconductor layer without implanting ions into a first region of the strained semiconductor layer and converting a portion of the crystalline semiconductor material in the second region of the strained semiconductor layer to amorphous material
Implementation Method 2
The amorphous region is recrystallized
Implementation Method 3
elements are diffused from one portion of the second region of the strained semiconductor layer into another portion of the strained semiconductor layer so as to enrich a concentration of the diffused elements
Data Source
AI summary
Methods of fabricating a semiconductor structure include implanting ion into a second region of a strained semiconductor layer on a multi-layer substrate to amorphize a portion of crystalline semiconductor material in the second region of the strained semiconductor layer without amorphizing a first region of the strained semiconductor layer. The amorphous region is recrystallized, and elements are diffused within the semiconductor layer to enrich a concentration of the diffused elements in a portion of the second region of the strained semiconductor layer and alter a strain state therein relative to a strain state of the first region of the strained semiconductor layer. A first plurality of transistor channel structures are formed that each comprise a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures are formed that each comprise a portion of the second region of the semiconductor layer.