Semiconductor Device Strained Channel Layer Stressor
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Solution Overview
Problem
The integration and operational reliability of two-dimensional non-volatile memory devices have reached limits, prompting the need for a three-dimensional structure with improved characteristics and manufacturing efficiency.
Innovation Solution
A semiconductor device with a stacked structure featuring alternately stacked conductive and insulating layers, a strained channel layer subjected to tensile stress by a stressor layer, and a core layer within the stressor layer, enhancing carrier mobility without altering physical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked perpendicular to the substrate to improve integration, then device density increases, but manufacturing complexity increases
Solution Approach 1:
The patent implements a nested structure where the strained channel layer is positioned within the stressor layer, which itself is integrated into the stacked memory cell structure. This nesting approach allows multiple functional layers to be combined in a compact arrangement, increasing device density while maintaining a systematic manufacturing process that forms layers sequentially through deposition and patterning steps.
Solution Approach 2:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. The channel layers are arranged perpendicular to the substrate in multiple stacked layers, enabling increased storage density by utilizing the vertical dimension. This dimensional change is achieved through alternating deposition of conductive and insulating layers followed by vertical patterning to form the stacked structure.
2Quantity of substance
If more memory cells are stacked to increase capacity, then integration improves, but carrier mobility decreases
Solution Approach 1:
The patent applies parameter changes by introducing mechanical stress through the stressor layer to modify the physical state of the channel layer. The stressor layer is designed with specific material properties and thickness to generate controlled tensile or compressive stress on the channel layer, which alters carrier mobility parameters. This allows the channel layer to maintain high carrier mobility even in vertically stacked three-dimensional structures where such degradation would normally occur.
3Reliability
If stressor layer is added to improve carrier mobility, then device performance improves, but structural complexity increases
Solution Approach 1:
The stressor layer serves multiple functions simultaneously: it provides mechanical stress to enhance carrier mobility in the channel layer, acts as a structural component in the stacked device architecture, and can be integrated with existing fabrication processes. By designing the stressor layer to fulfill multiple roles within the device structure, the patent reduces the need for additional separate components, thereby limiting the increase in structural complexity while achieving improved carrier mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves carrier mobility and maintains high current intensity even with increased memory cell stacking, enhancing the semiconductor device's performance and manufacturing ease.
Implementation Method 1
a strained channel layer surrounding an outer surface of the stressor layer and having a different thermal expansion coefficient than the stressor layer
Implementation Method 2
forming a strained channel layer by performing heat treatment of the stressor layer and the channel layer
Data Source
AI summary
A semiconductor memory device includes a stacked structure including conductive layers and insulating layers alternately stacked, a strained channel layer passing through the stacked structure, a stressor layer contacting the strained channel layer and applying stress to the strained channel layer, and a core layer formed in the stressor layer.