Semiconductor String Select Line Resistance Reduction via Strapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and reducing the resistance of string select lines, which affects their performance and efficiency.
Innovation Solution
The semiconductor device design includes a plurality of word lines and a string select line on a substrate, with memory strings extending in a direction through both, and a strapping line connected to the string select line, which functions as a bypass wire or shunt structure to reduce the resistance of the string select lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements three-dimensional memory cell arrangement by stacking multiple layers of memory cells vertically, transitioning from two-dimensional planar arrangement to three-dimensional vertical stacking. This enables increased storage capacity by utilizing the vertical dimension, allowing multiple bit lines and word lines to be stacked in different layers while maintaining electrical connectivity through vertical channels and select lines that penetrate through the stacked structure.
Solution Approach 2:
The patent employs nested structure where multiple memory cell layers are stacked within a single memory block, with each layer containing memory cells formed between bit lines and word lines. The select lines penetrate through multiple layers to control memory cells in different stacks, creating a nested configuration where smaller memory cell units are contained within larger memory block structures, efficiently utilizing vertical space.
2Quantity of substance
If string select line length is increased to cover more memory cells, then data storage capacity is improved, but wiring resistance increases
Solution Approach 1:
The patent divides the string select line into multiple separate select lines, each controlling a specific stack or group of memory cells. Instead of using a single long select line that would have high resistance, multiple shorter select lines are implemented, with each line having lower resistance. This segmentation allows efficient control of memory cells in different vertical stacks while maintaining low wiring resistance in each individual select line.
Solution Approach 2:
The patent introduces select lines as intermediary conductive elements that connect the control circuitry to memory cells in vertical stacks. These select lines act as mediators between the bit lines/word lines and the memory cell transistors, enabling voltage application to specific memory cells for read, program, and erase operations while providing low-resistance electrical pathways through the three-dimensional structure.
Data Source
AI summary
A semiconductor device includes word lines disposed on a substrate and spaced apart in a first direction perpendicular to an upper surface of the substrate, a string select line disposed on the word lines, memory strings extending in the first direction on the substrate, each memory string including a first channel extending in the first direction through the word lines, and memory cells constituted by the word lines around the first channel, bit lines electrically connected to the memory strings, and a strapping line connected to the string select.