Semiconductor Device Stress Dispersion at Insulating Layer Openings
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Solution Overview
Problem
Semiconductor devices with three-dimensional stacked structures face issues with cracking of wiring on printed wiring substrates due to stress from temperature changes, particularly at the edges of openings in insulating layers, where differences in linear expansion coefficients between materials lead to concentrated stress and potential wire breakage.
Innovation Solution
The semiconductor device incorporates a printed wiring substrate with a wiring layer, a first insulating layer featuring protrusion or recess portions along the edges of openings to disperse stress, and a second insulating layer that covers the semiconductor chip and bonding wires, using a sealing resin layer with inorganic fillers to manage stress and prevent cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional stacked structure is adopted to increase integration, then device functionality and speed are improved, but stress concentration at opening edges causes wiring cracks and reliability degradation
Solution Approach 1:
The patent applies local quality by providing protrusion portions or recess portions specifically at the edges of openings where stress concentrates, rather than uniformly modifying the entire insulating layer. This localized structural modification targets the specific problem area (opening edges) to disperse stress and prevent wiring cracks, while maintaining the overall three-dimensional stacked structure for high integration.
2Ease of manufacture
If conventional insulating layer structure is used, then manufacturing is simple, but stress concentration at opening edges causes wiring cracks
Solution Approach 1:
The insulating layer is modified with localized protrusion portions or recess portions at opening edges, combining simple overall structure with targeted local modifications. This approach maintains ease of manufacture through standard semiconductor fabrication processes while significantly improving wiring integrity by dispersing stress at critical locations.
Solution Approach 2:
The protrusion portions or recess portions create curved or non-linear edge profiles at openings, replacing sharp corners with gradual transitions. This curvature reduces stress concentration by distributing mechanical stress more evenly across the opening edges, preventing wiring cracks while maintaining manufacturing feasibility.
3Manufacturing precision
If opening edges are sharp and straight, then manufacturing precision is easier to control, but stress concentrates at edges causing insulating layer peeling
Solution Approach 1:
The patent introduces curved edge profiles through protrusion portions or recess portions, replacing sharp straight edges. This curvature reduces stress concentration points, preventing insulating layer peeling while remaining compatible with standard photolithography and etching processes used in semiconductor manufacturing.
Solution Approach 2:
The protrusion portions or recess portions are formed in advance during insulating layer fabrication, before wiring deposition and device assembly. This preliminary structural modification pre-empts stress concentration issues, ensuring wiring and insulating layer integrity throughout subsequent manufacturing steps and device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively disperses stress along the edges of openings, reducing the likelihood of wiring cracks and peeling of insulating layers, thereby enhancing the reliability and durability of semiconductor devices by managing thermal expansion differences between materials.
Implementation Method 1
differences in linear expansion coefficients between materials lead to concentrated stress
Data Source
AI summary
According to one embodiment, a semiconductor device includes: a printed wiring substrate that includes a substrate, a wiring layer on the substrate, and a first insulating layer on the wiring layer. The wiring layer includes a connection terminal and a wiring electrically connected to the connection terminal. The first insulating layer includes an opening that exposes at least a portion of the connection terminal and at least a portion of the wiring, and at least one of a protrusion portion or a recess portion, provided along an edge of the opening, that overlaps the wiring. The semiconductor device includes a semiconductor chip mounted on the printed wiring substrate; a bonding wire that electrically connects the connection terminal and the semiconductor chip; and a second insulating layer that covers the semiconductor chip, the bonding wire, and the opening.