Stress Engineering in Semiconductor Contacts via Metal Nitride Layers
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to enhance transistor performance by increasing charge carrier mobility while maintaining high internal stress levels in dielectric materials, especially in densely packed device regions where layer thickness is limited, leading to deposition-related irregularities and reduced strain-inducing effects.
Innovation Solution
The use of highly stressed non-insulating material layers, such as metal nitrides, is implemented with a material layer stack comprising a first dielectric layer, a strain-inducing non-insulating layer, and a second dielectric layer, where the strain-inducing layer is patterned and laterally isolated by spacer elements to induce strain in the semiconductor region without affecting contact element configuration, allowing for reduced layer thickness and improved deposition compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If highly stressed dielectric material layers are used to induce strain in the channel region, then charge carrier mobility is enhanced, but layer thickness must be increased to achieve sufficient stress levels, which causes deposition-related irregularities in densely packed device regions
Solution Approach 1:
The patent changes the material parameter from conventional dielectric materials to metal nitride materials that can generate equivalent or superior stress levels at significantly reduced thickness (e.g., 5-20 nm vs. 50-200 nm), thereby maintaining strain induction effectiveness while eliminating deposition irregularities in densely packed regions
Solution Approach 2:
The patent employs composite material structures where metal nitride layers are integrated with dielectric layers to form a hybrid stress-inducing system, combining the high stress density of metals with the insulating properties of dielectrics, enabling effective strain engineering without electrical interference
2Stress or pressure
If the layer thickness of stressed dielectric material is increased to maintain high internal stress levels, then strain-inducing effects are enhanced, but deposition-related irregularities occur in densely packed device regions
Solution Approach 1:
The patent fundamentally changes the material composition parameter to metal nitrides, which possess inherently higher stress density per unit thickness, allowing the achievement of high internal stress levels (e.g., >1 GPa) at ultrathin dimensions that are fully compatible with standard deposition processes even in densely packed configurations
3Reliability
If conventional dielectric materials are used for stress engineering, then electrical insulation is maintained, but higher layer thickness is required to achieve sufficient stress levels, leading to deposition irregularities
Solution Approach 1:
The patent transforms the material parameter from conventional dielectrics to metal nitrides, achieving a paradigm shift where ultrathin layers (5-20 nm) provide equivalent or superior stress induction compared to thick dielectric layers, thereby simplifying the overall layer structure and reducing the number of process steps required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables superior strain-inducing effects with high internal stress levels up to 9 GPa, enhancing transistor performance even in critical dimensions of 40 nm and less, while maintaining robustness against misalignments and deposition irregularities, thus extending stress engineering to further device generations.
Implementation Method 1
the strain-inducing non-insulating material layer induces a strain in the semiconductor region
Implementation Method 2
a spacer element formed on the sidewalls of the opening so as to laterally isolate the strain-inducing non-insulating material layer
Data Source
AI summary
In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.