Semiconductor Stress Engineering for Carrier Mobility
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Solution Overview
Problem
Current semiconductor device fabrication methods do not effectively enhance carrier mobility in MOSFET channels, which limits the current flow and device performance.
Innovation Solution
The method involves forming stressor regions with stressor material incorporated into substitutional sites in the substrate, followed by a low-temperature anneal to memorize stress, and the use of a stressor layer with lateral portions adjacent to the substrate surface, enhancing stress induction on the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used, then manufacturing simplicity is maintained, but carrier mobility enhancement is insufficient
Solution Approach 1:
Stressor material is incorporated into substitutional sites during the epitaxial growth process before device fabrication, and a stressor layer is deposited beforehand to provide preliminary stress. This preliminary stress is then memorized during annealing, enabling carrier mobility enhancement without requiring complex post-processing steps.
Solution Approach 2:
The patent utilizes changes in material parameters during annealing (temperature, time, atmosphere) to memorize stress in the semiconductor substrate. By controlling annealing parameters, the stress state is preserved and transferred to the channel region, enhancing carrier mobility without adding fabrication complexity.
2Reliability
If stressor material is incorporated into substitutional sites, then carrier mobility is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The epitaxial growth process automatically incorporates stressor material into substitutional sites through self-diffusion mechanisms during controlled annealing. The stressor atoms migrate and occupy substitutional positions without requiring precise external positioning, reducing manufacturing precision requirements while maintaining carrier mobility enhancement.
3Reliability
If a stressor layer with lateral portions is used, then stress induction on channel is enhanced, but device complexity increases
Solution Approach 1:
The stressor layer is designed with lateral portions that extend beyond the gate stack, creating localized stress regions. The lateral portions provide additional stress induction in the channel region while the structure remains integrated with the existing device architecture, enhancing drive current without proportionally increasing device complexity.
4Reliability
If low-temperature anneal is performed, then stress memorization is achieved, but energy input is reduced
Solution Approach 1:
The patent utilizes changes in material parameters during annealing (temperature, time, atmosphere) to memorize stress in the semiconductor substrate. By controlling annealing parameters, the stress state is preserved and transferred to the channel region, enhancing carrier mobility without adding fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases carrier mobility, improving drive current and reducing sub-threshold leakage, leading to better semiconductor device performance.
Implementation Method 1
methods for improving carrier mobility in semiconductor devices using stress engineering
Implementation Method 2
an anneal carried out to memorize at least a portion of the first stress value in the semiconductor device
Data Source
AI summary
A method for fabricating a semiconductor device is presented. The method comprises providing a gate stack including a gate dielectric and gate electrode over a substrate. Stressor regions comprising stressor material incorporated into substitutional sites of the substrate are formed within the substrate on opposed sides of the gate stack. A first stressor layer having a first stress value is formed over the semiconductor device after forming the stressor regions followed by an anneal to memorize at least a portion of the first stress value in the semiconductor device, wherein the anneal is conducted at a low temperature.