Semiconductor Stress Layer Protection via Contact-Hole Etch Stop
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Solution Overview
Problem
Existing semiconductor fabrication methods face challenges in forming stress layers without damaging them, which affects the performance and reliability of semiconductor structures due to the short channel effect and increased circuit density, leading to degraded performance and limited size reduction of semiconductor devices.
Innovation Solution
A method involving the formation of stress layers on both sides of gate structures with specific mask layers and contact-hole etch stop layers to protect and expose the stress layers during the fabrication process, ensuring minimal damage and maintaining performance, including the use of atomic layer deposition for conformal coverage and high-density mask layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple plugs are formed in a semiconductor structure containing a stress layer, then interconnection requirements are met, but the stress layer is damaged and performance degrades
Solution Approach 1:
A contact-hole etch stop layer is introduced as an intermediary protective layer between the stress layer and the etching process. This etch stop layer prevents direct contact between the etchant and the stress layer, thereby protecting the stress layer from damage while still allowing the formation of contact holes for interconnection.
Solution Approach 2:
The contact-hole etch stop layer is formed preliminarily before the contact hole etching process. This preliminary action ensures that the stress layer is protected in advance before any damaging etching occurs, allowing subsequent plug formation without compromising stress layer integrity.
2Productivity
If channel length is reduced to increase circuit density, then more components fit on the wafer, but short channel effects become prominent and device performance degrades
Solution Approach 1:
The patent changes the physical parameters of the channel region by introducing stress layers with specific stress characteristics. This modifies the electrical properties of the semiconductor material, enabling shorter channel lengths to maintain acceptable performance by compensating for short channel effects through stress-induced mobility enhancement.
Solution Approach 2:
The patent uses composite material structures including stress layers composed of different semiconductor materials (e.g., SiGe, SiC) combined with silicon. These composite structures provide both the mechanical stress needed to counteract short channel effects and the electrical properties required for high-performance transistors at reduced dimensions.
3Reliability
If stress layers are introduced to improve carrier mobility, then transistor performance improves, but the fabrication process becomes more complex
Solution Approach 1:
The contact-hole etch stop layer is merged with the stress layer structure, serving dual functions: protecting the stress layer during fabrication and acting as part of the overall device architecture. This integration reduces the need for separate protective layers and simplifies the fabrication process despite the added functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces damage to stress layers, improves the performance and reliability of semiconductor structures, and allows for further size reduction of semiconductor devices by maintaining the integrity of the stress layers during the fabrication process.
Implementation Method 1
forming a contact-hole etch stop layer on the second stress layer... removing at least a portion of the contact-hole etch stop layer exposed at the bottom of each first contact hole
Implementation Method 2
forming a first-region mask layer on the first stress layer... removing the first-region mask layer at the bottom of each first contact hole
Implementation Method 3
the use of atomic layer deposition for conformal coverage and high-density mask layers
Data Source
AI summary
A method for fabricating a semiconductor structure includes forming a plurality of first gate structures on a first region of a substrate, a plurality of second gate structures on a second region of the substrate, and a first stress layer on both sides of each first gate structure; forming a first-region mask layer on the first stress layer; forming a second stress layer on both sides of each second gate structure; forming a contact-hole etch stop layer on the second stress layer; forming a plurality of first contact holes on the first stress layer and a plurality of second contact holes on the second stress layer to expose the contact-hole etch stop layer; at least partially removing the contact-hole etch stop layer in each first contact hole; and removing the first-region mask layer in each first contact hole and the contact-hole etch stop layer in each second contact hole.