Semiconductor Stress Layer Formation for Charge Mobility
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Solution Overview
Problem
Current semiconductor manufacturing methods face challenges in achieving high integration density and performance due to limitations in stress application on channel regions, which can lead to reduced charge mobility and increased resistance in gate and source/drain regions.
Innovation Solution
The method involves forming multiple stress layers, specifically silicon nitride layers, on a semiconductor substrate to apply consistent tensile or compressive stress on the channel region, with each stress layer being formed and removed multiple times to achieve high stress levels without damaging underlying layers, using techniques like ion bombardment and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single stress layer is formed on the substrate, then the manufacturing process is simple, but the stress level applied to the channel region is insufficient to enhance charge mobility
Solution Approach 1:
The stress application process is divided into multiple discrete stress layer formation steps. Each stress layer is formed, patterned, and removed sequentially to apply stress in controlled increments. This segmentation allows achieving high cumulative stress levels while maintaining process control and preventing damage to underlying layers.
Solution Approach 2:
The stress layer formation is performed periodically through multiple cycles. Each cycle consists of forming a stress layer, patterning it to expose specific regions, and removing it. This periodic action enables cumulative stress application to the channel region while allowing recovery and control between cycles, preventing material damage.
2Reliability
If high stress is applied to the channel region to improve charge mobility, then device performance is enhanced, but underlying layers may be damaged
Solution Approach 1:
Each individual stress layer is formed with thickness and stress level that would be insufficient alone, but when applied cumulatively through multiple cycles, achieves the desired high stress level. This partial action approach allows building up stress gradually without exceeding damage thresholds in any single step, protecting the metal silicide regions while achieving high charge mobility.
3Reliability
If multiple stress layers are formed and removed sequentially, then high stress levels are achieved without damaging underlying layers, but the manufacturing process time increases
Solution Approach 1:
Multiple stress layer formation cycles are merged into a unified manufacturing sequence with shared process steps. The patterning and removal steps are consolidated and optimized across cycles, and process parameters are adjusted to reduce cycle times. This merging approach minimizes the cumulative time penalty while maintaining the benefits of multiple stress applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge mobility and drain current characteristics while maintaining the integrity of the metal silicide regions, improving the overall performance and reliability of semiconductor devices.
Implementation Method 1
Both the first stress layer and the second stress layer may provide a same type of stress from among a compressive stress and a tensile stress such that the first and second stress layers exert the same type of stress on a channel region
Implementation Method 2
Depositing the silicon nitride for forming the first stress layer and depositing the silicon nitride for forming the second stress layer may include performing ion bombardment on the silicon nitride
Implementation Method 3
Depositing the silicon nitride for forming the first stress layer and depositing the silicon nitride for forming the second stress layer may include performing ion bombardment on the silicon nitride
Implementation Method 4
forming a buffer layer including a material having etch selectivity with respect to each of the first stress layer and the second stress layer
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate.