Semiconductor Stress Layer Lattice Mismatch Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor manufacturing processes result in high defectivity in source and drain regions, leading to increased contact resistance and adverse effects on transistor properties and performance due to high lattice mismatch and defect formation in stress layers.
Innovation Solution
A method involving the formation of a semiconductor device with a stress layer, an interlayer, and a capping layer, where the interlayer is deposited at a lower rate than the capping layer to reduce defects and improve lattice mismatch, thereby enhancing the quality of the capping layer and transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stress layer is formed using conventional semiconductor manufacturing processes, then carrier mobility in the channel region is improved, but defect density in the stress layer increases
Solution Approach 1:
The stress layer is divided into multiple sub-layers with different materials and thicknesses. The first stress layer is formed with a first material having a first thickness, and the second stress layer is formed with a second material having a second thickness. This segmentation allows optimization of stress distribution while reducing defect formation at any single interface.
Solution Approach 2:
A capping layer is introduced as an intermediary between the stress layers and the channel region. This capping layer acts as a buffer that reduces the direct impact of lattice mismatch between the stress layers and the channel region, thereby reducing defect density while maintaining the stress-induced carrier mobility improvement.
2Reliability
If the thickness of the stress layer is increased to improve hole mobility, then compressive stress on the channel region increases, but defect formation increases
Solution Approach 1:
The total stress layer thickness is segmented into multiple sub-layers with different thicknesses. The first stress layer has a first thickness and the second stress layer has a second thickness, allowing the total effective thickness to be increased for improved hole mobility while distributing the stress and reducing defect formation that would occur with a single thick layer.
Solution Approach 2:
Different regions of the stress layer structure have different local properties. The first and second stress layers have different materials and thicknesses tailored to provide optimal stress distribution. The capping layer provides local protection at the interface with the channel region, reducing defect formation in critical areas while maintaining overall stress effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach reduces defects and improves the quality of the capping layer, leading to enhanced transistor properties and performance by minimizing lattice mismatch and contact resistance.
Implementation Method 1
a lattice mismatch between the interlayer and the capping layer is lower than a lattice mismatch between the capping layer and the stress layer
Implementation Method 2
By applying compressive stress on a channel region of a transistor, hole mobility in the channel region may be improved
Implementation Method 3
The lattice constant of the strained material is often greater than the lattice constant of the material in the channel region. Thus, the strained material can apply compressive stress on channel region of the PMOS transistor
Data Source
AI summary
The present disclosure provides a method for forming a semiconductor device. The method includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and forming trenches in the semiconductor substrate on both sides of the gate structure. The method also includes forming a stress layer on inner sidewalls of each trench to fill up the trench; forming an interlayer on the stress layer, and forming a capping layer on the interlayer, wherein a top surface of the capping layer is higher than a top surface of the semiconductor substrate, and a lattice mismatch between the interlayer and the capping layer is lower than a lattice mismatch between the capping layer and the stress layer.