Semiconductor Stress Layer Offset for Carrier Mobility

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Solution Overview

Problem

Conventional dual etch-stop layers used in semiconductor devices to generate compressive or tensile stress can degrade the performance of these devices, necessitating an optimized arrangement of tensile and compressive layer regions to enhance carrier mobility within channel regions.

Innovation Solution

The integration of tensile and compressive layer regions in semiconductor devices, where the layers are strategically positioned and offset relative to the channel region in both lateral and transverse directions, with specific materials like oxides, nitrides, or oxynitrides, and deposited using techniques such as PECVD to control stress levels, while using isolation regions with varying stress types and distances to optimize performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stress or pressure

If conventional dual etch-stop layers are used to generate compressive or tensile stress, then stress can be applied to channel regions, but device performance degrades

Engineering Contradiction:
Improvestress on channel regionsVSAvoiddevice performance
Core Design Contradiction:
Stress or pressureVSReliability

Solution Approach 1:

The patent divides the stress application into separate tensile and compressive layer regions that are spatially segmented and offset from each other. This segmentation allows different regions to experience different stress types without the negative interactions that occur with conventional dual etch-stop layers, thereby maintaining device performance while achieving stress enhancement.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different stress characteristics (tensile vs. compressive) to different local regions of the semiconductor device. By creating tensile layer regions and compressive layer regions with offset configurations, each region receives optimized stress treatment tailored to its specific requirements, improving overall device performance without degradation.

Inventive Principle:
Principle #3Local quality

2Stress or pressure

If tensile and compressive layers are positioned closer to channel region, then stress effect increases, but device performance may degrade due to improper stress distribution

Engineering Contradiction:
Improvestress effect on channel regionVSAvoiddevice performance
Core Design Contradiction:
Stress or pressureVSReliability

Solution Approach 1:

The patent employs asymmetric positioning of tensile and compressive layers relative to the channel region. The layers are offset from each other in a controlled manner, creating an asymmetric stress distribution pattern that maximizes the beneficial stress effect on carrier mobility while avoiding the performance degradation that results from symmetric or improperly distributed stress configurations.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent extends the stress application beyond a single plane by positioning tensile and compressive layers at different lateral offsets and potentially different vertical positions. This multi-dimensional arrangement allows optimization of stress distribution in both lateral and vertical dimensions, enhancing carrier mobility while maintaining device performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances carrier mobility by optimizing stress distribution, leading to improved performance of semiconductor devices by balancing and maximizing tensile and compressive stresses across different regions.

Implementation Method 1

deposited using techniques such as PECVD to control stress levels

Methodology Applied
Scientific EffectPlasma Enhanced Chemical Vapour Deposition: Plasma Enhanced Chemical Vapour Deposition

Implementation Method 2

a first region of the isolation region is under a stress of a first type, wherein the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type

Methodology Applied
Scientific EffectMechanical Stress: Mechanical Force

Data Source

PatentUS9847389B2Semiconductor device including an active region and two layers having different stress characteristics
Publication Date: 2017.12.19 NXP USA INC
  • US9847389B2 patent drawing
  • US9847389B2 patent drawing
  • US9847389B2 patent drawing

AI summary

An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.