Semiconductor Stress Layer Segmentation for Leakage Control
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Solution Overview
Problem
The performance of semiconductor structures is hindered by the short-channel effect and leakage current issues due to weak gate-to-channel control and reduced carrier mobility, particularly as device sizes decrease, leading to stress-released issues and increased doping concentrations that exacerbate these problems.
Innovation Solution
A method involving the formation of a first stress layer before and a second stress layer after the gate structure, with the second stress layer formed after the gate structure to minimize the impact of gate formation processes and reduce stress-released issues, enhancing carrier mobility and suppressing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stress layer is formed in the base substrate to improve carrier mobility, then carrier mobility is enhanced, but stress is released during gate formation processes, reducing the effectiveness of the stress layer
Solution Approach 1:
The stress layer is divided into multiple segments: a first stress layer formed before gate structure fabrication, and a second stress layer formed after gate structure fabrication. This segmentation allows each stress layer to serve different functional purposes - the first provides initial stress and the second restores stress after gate formation processes cause stress release, thereby maintaining effective stress on the channel throughout the device lifecycle.
Solution Approach 2:
The first stress layer is formed preliminarily before the gate structure fabrication process. This preliminary stress layer provides initial carrier mobility enhancement and prepares the device structure for subsequent processing. The stress layer is formed in advance to establish the stress state before the gate formation processes that would subsequently release this stress.
2Productivity
If gate dimensions are scaled down to increase component density, then integration degree is improved, but gate-to-channel control capability weakens, causing short-channel effect and leakage current
Solution Approach 1:
The invention transitions from planar gate control to three-dimensional FinFET structure with multi-gate control. The gate electrode wraps around the fin from multiple sides (at least two sides), providing enhanced gate-to-channel control capability in additional spatial dimensions. This dimensional change allows maintaining strong control even as device dimensions are scaled down, effectively suppressing short-channel effects while enabling higher component density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of semiconductor structures by maintaining effective stress on the channel, reducing contact resistance, and controlling the short-channel effect, thereby enhancing carrier mobility and overall device performance.
Implementation Method 1
Because stress can change an energy gap and the carrier mobility of a silicon material, the performance of the transistor is commonly improved by forming a stress layer.
Data Source
AI summary
A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate, and forming a first stress layer in the base substrate. The method also includes forming a gate structure on the base substrate. The first stress layer in the base substrate is on both sides of the gate structure. In addition, the method includes after forming the gate structure, forming an opening in the first stress layer by back-etching the first stress layer. Further, the method includes forming a second stress layer in the opening of the first stress layer.