Semiconductor Stress Layer Spacing via Cover Layer Etching
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Solution Overview
Problem
As semiconductor device dimensions decrease, the formation of self-aligned silicide becomes challenging, leading to increased contact resistance and decreased performance of MOS transistors, particularly due to the close spacing between stress layers which can result in short-circuit issues.
Innovation Solution
The process involves forming stress layers with a germanium-silicon material, creating a Sigma-shaped opening, and using an etching gas like hydrogen chloride to remove portions of the cover layer on adjacent side surfaces, thereby increasing the spacing between stress layers and preventing short-circuits, followed by forming a nickel metal layer to react with the cover layer and form a silicide layer, reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-aligned silicide is formed using conventional processes, then contact resistance is reduced, but the process becomes difficult to implement as device dimensions decrease
Solution Approach 1:
The patent segments the stress layer formation process by creating separate first and second stress layers with a cover layer between them. This segmentation allows independent control and spacing of the stress layers, making the self-aligned silicide formation process feasible at reduced dimensions by preventing short-circuits while maintaining low contact resistance.
Solution Approach 2:
The patent applies preliminary action by forming the cover layer between the stress layers before the self-aligned silicide formation process. This preliminary placement of the cover layer prevents short-circuits during subsequent processing steps, enabling the self-aligned silicide to be formed successfully at smaller dimensions.
2Speed
If stress layers are placed close together to improve device performance, then operating speed is improved, but short-circuit issues occur
Solution Approach 1:
The patent introduces a cover layer as an intermediary between the first and second stress layers. This intermediary structure physically separates the stress layers, preventing short-circuits while allowing them to remain close enough to maintain improved carrier mobility and operating speed in the channel region.
3Area of stationary object
If device dimensions are reduced to improve integration density, then chip area is reduced, but contact resistance increases
Solution Approach 1:
The patent changes the structural parameters by introducing a cover layer with specific material composition and thickness between the stress layers. This parameter modification enables the formation of reliable self-aligned silicide contacts at reduced dimensions by controlling the spacing and preventing short-circuits, thereby maintaining low contact resistance despite smaller device footprints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces contact resistance and prevents short-circuit issues by increasing the spacing between stress layers and improving the formation of self-aligned silicide, enhancing the performance of MOS transistors.
Implementation Method 1
using an etching gas to etch and remove the cover layer formed on the adjacent side surfaces of the first stress layer and the second stress layer
Implementation Method 2
forming a metal layer on the silicon layer by an evaporation process, or a sputtering process; performing an annealing process, thus the metal and silicon can react with each other to form metal silicide
Implementation Method 3
The source region and the drain region of the MOS transistor made of germanium silicon material or carbon silicon material can introduce compressive stress or tensile stress in the channel region of the MOS transistor
Data Source
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AI summary
A method is provided for fabricating a semiconductor structure. The method includes providing a substrate including a first region for forming a first transistor and a second region for forming a second transistor. The method also includes forming a first stress layer in the substrate in the first region and a second stress layer in the substrate in the second region, wherein top surfaces of the first stress layer and the second stress layer are above a surface of the substrate. Further, the method includes forming a cover layer on each of the first stress layer and the second stress layer, and removing portions of the cover layer formed on adjacent side surfaces of the first stress layer and the second stress layer.