Semiconductor Stress Layers Near Active Region
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Solution Overview
Problem
The formation of stress layers in semiconductor devices often results in surface damage to active regions, particularly during the removal of gate spacers, which can lead to reduced stress effect and increased resistance, causing issues like punch-through phenomena.
Innovation Solution
A method of forming stress layers closer to the active region by removing second gate spacers without causing etching damage, using buffer layers to improve interfacial contact and prevent distortion, and forming stress layers on gate silicide regions, source/drain regions, and silicide regions to maintain original heights and reduce surface recess.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If stress layers are formed closer to the active region to increase stress effect, then stress effect is improved, but etching damage to the active region increases
Solution Approach 1:
The patent applies preliminary action by forming a protective layer on the active region before removing the gate spacer. This protective layer is formed in advance to prevent etching damage that would occur during the subsequent gate spacer removal process, allowing the stress layer to be formed closer to the active region without causing surface damage.
Solution Approach 2:
The patent uses an intermediary protective layer that acts as a mediator between the etching process and the active region. This intermediate layer absorbs the harmful etching effects while allowing the stress layer to be positioned optimally close to the active region for maximum stress effect.
2Stress or pressure
If gate spacers are removed to form stress layers closer to active region, then stress effect is improved, but surface recess and resistance increase
Solution Approach 1:
The protective layer is formed preliminarily before gate spacer removal to prevent surface recess. By having this protective layer in place beforehand, the active region surface maintains its original height and flatness even after the gate spacer is removed and the stress layer is formed closer by.
3Object-affected harmful factors
If stress layers are formed with gate spacers present, then etching damage is reduced, but stress effect decreases
Solution Approach 1:
The patent segments the protective function from the gate spacer structure itself by forming a separate protective layer. This allows the gate spacer to be removed for optimal stress layer positioning while the separate protective layer continues to prevent etching damage, resolving the conflict between maintaining protection and achieving optimal stress effect.
Data Source
AI summary
A semiconductor device according to example embodiments may include a substrate having an NMOS area and a PMOS area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the isolation regions, source/drain silicide regions formed in the source/drain regions, a tensile stress layer formed on the NMOS area, and a compressive stress layer formed on the PMOS area, wherein the tensile stress layer and compressive stress layer may overlap at a boundary region of the NMOS area and the PMOS area. The semiconductor devices according to example embodiments and methods of manufacturing the same may increase the stress effect on the active region while reducing or preventing surface damage to the active region.