Semiconductor Stress-Applying Layers for Carrier Mobility
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Solution Overview
Problem
In semiconductor devices, applying stress to the channel part to enhance carrier mobility is hindered by the weakening effect of the gate electrode, and high concentrations of Ge or C in stress-applying layers can lead to defects and increased junction leakage.
Innovation Solution
The semiconductor device incorporates stress-applying layers with a different lattice constant epitaxially grown on both sides of the gate electrode, positioned deeper than the surface, allowing for intensive stress application to the channel part by digging down the substrate, thereby improving carrier mobility without relying on high Ge or C concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If stress-applying layers with high Ge or C concentrations are used to enhance carrier mobility, then carrier mobility is improved, but defects increase and junction leakage increases
Solution Approach 1:
The patent applies local quality by creating stress-applying layers with different material compositions at different locations. Specifically, SiGe layers are formed on one side of the channel and SiC layers on the other side, each tailored to provide appropriate stress characteristics locally without requiring high concentrations throughout the entire structure
Solution Approach 2:
The patent changes the material composition parameters by using SiGe and SiC with controlled, low concentrations of Ge and C respectively. This allows stress application while maintaining lower impurity levels compared to conventional high-concentration approaches, thus reducing defects and leakage while still achieving mobility enhancement
2Ease of operation
If gate electrode is present to control the transistor, then transistor control is achieved, but stress application to channel part is weakened
Solution Approach 1:
The patent resolves this contradiction by transitioning from planar stress application to three-dimensional stress application. Stress-applying layers are formed extending vertically from the channel region, applying stress from multiple directions and depths rather than just at the surface level, thereby overcoming the gate electrode's blocking effect in the planar direction
3Ease of manufacture
If conventional manufacturing process is used, then manufacturing simplicity is maintained, but stress application effectiveness is reduced
Solution Approach 1:
The patent applies segmentation by dividing the stress application function into separate, modular components. SiGe and SiC stress-applying layers are formed as distinct structures on opposite sides of the channel, allowing independent optimization and formation processes while achieving cumulative stress effects that would be difficult with a single monolithic structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively applies stress to the channel part, enhancing carrier mobility and reducing defects, while maintaining low Ge or C concentrations to prevent leakage issues.
Implementation Method 1
stress-applying layers with a different lattice constant epitaxially grown on both sides of the gate electrode
Implementation Method 2
applying stress to the channel part to enhance carrier mobility
Data Source
AI summary
A method of manufacturing a semiconductor device in which a stress can be effectively applied from a semiconductor layer having a different lattice constant from a semiconductor substrate to a channel part, whereby carrier mobility can be improved and higher functionality can be achieved.