Semiconductor Device Stress Distribution Mount Bed

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Solution Overview

Problem

Semiconductor devices under high voltage and high current conditions face surface cracking due to internal stress caused by thermal expansion coefficient differences in package materials, which can lead to element breakdown.

Innovation Solution

A semiconductor device design where the first switching element is sealed in a resin package with a specific arrangement that reduces stress by positioning it centrally between side surfaces, using a mount bed to distribute stress isotropically and prevent concentration, and employing resins with different thermal expansion coefficients to compression-seal the components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the semiconductor chip surface area is enlarged to increase current capacity under high voltage and high current conditions, then the current capacity is improved, but the chip becomes more susceptible to breaking due to internal stress from thermal expansion coefficient differences

Engineering Contradiction:
Improvecurrent capacityVSAvoidchip breakage resistance
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent divides the semiconductor device into distinct functional modules: a first semiconductor chip containing switching elements, a second semiconductor chip containing light-receiving elements, and a light-emitting element. These modules are arranged in separate regions within the package, allowing stress distribution and reducing the risk of complete device failure. The segmentation also enables independent optimization of each module's thermal and mechanical properties.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a light-based communication mechanism as an intermediary between the first and second semiconductor chips. Electrical signals are converted to optical signals by the light-emitting element and detected by the light-receiving element, creating an isolated communication path that reduces direct electrical stress and thermal coupling between high-power switching elements and sensitive receiving elements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If package materials with different thermal expansion coefficients are used, then the packaging flexibility and component compatibility are improved, but internal stress increases causing surface cracking and element breakdown

Engineering Contradiction:
Improvepackage material compatibilityVSAvoidinternal stress and cracking
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies different material properties to different regions of the package. The first and second semiconductor chips are positioned in regions with optimized thermal expansion characteristics, while the resin package material is selected to provide mechanical support in high-stress areas. This local optimization allows the use of materials with different thermal expansion coefficients without causing widespread cracking.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent designs the package structure to anticipate and compensate for thermal expansion differences before they cause damage. The resin package is formulated with specific mechanical properties that absorb and distribute thermal stress, and the component layout is optimized to create stress relief zones that prevent crack propagation during temperature cycling.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Power

If the semiconductor chip surface area is increased to handle high voltage and current, then the power handling capability is improved, but the device complexity and stress management difficulty increase

Engineering Contradiction:
Improvevoltage and current handling capabilityVSAvoidstress distribution complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent transitions from a planar arrangement to a three-dimensional stacked configuration. The first semiconductor chip, second semiconductor chip, and light-emitting element are arranged in vertical layers, allowing high power handling capability in a compact footprint. This dimensional change simplifies stress management by separating high-stress switching elements from sensitive receiving elements in the vertical dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively reduces stress on the semiconductor elements, preventing breakdown and enhancing the package's rigidity against deformation, thereby ensuring stable operation under high voltage and current conditions.

Implementation Method 1

the semiconductor chip is sealed in a resin package, and may be broken by internal stress due to the thermal expansion coefficient difference of package materials

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20220262779A1Semiconductor device
Publication Date: 2022.08.18 KK TOSHIBA
  • US20220262779A1 patent drawing
  • US20220262779A1 patent drawing
  • US20220262779A1 patent drawing

AI summary

A semiconductor device includes a light-emitting element, a light-receiving element, an input-side terminal, a first switching element, a first lead and a resin package. The first lead includes a first mount bed and a first output-side terminal, the first switching element being mounted on the first mount bed. The resin package seals the light-emitting element, the light-receiving element, and the first switching element. The resin package includes first and second side surfaces opposite to each other. The input-side terminal protrudes from the first side surface. The first output-side terminal protrudes from the second side surface. The first switching element is sealed at a center between the first and second side surfaces. The first mount bed is arranged in a direction along the second side surface so that a side surface of the first mount bed is positioned between a center of the resin package and the first output-side terminal.