Semiconductor Package Stress Relax Pattern

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Solution Overview

Problem

Wafer level packaging faces challenges due to warpage caused by coefficient of thermal expansion (CTE) mismatch and thickness of the molding compound, leading to increased stress on semiconductor device packages.

Innovation Solution

A pattern of dielectric material with a lower Young's modulus and CTE than the mold compound is formed around metal contacts on the die, surrounded by the mold compound, and a redistribution layer is added to connect to the metal contacts after grinding, reducing stress and warpage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a thick layer of molding compound is used to cover the wafer and dies, then the packaging thickness is increased providing better protection, but warping is increased due to CTE mismatch

Engineering Contradiction:
ImproveprotectionVSAvoidwarping
Core Design Contradiction:
StrengthVSShape

Solution Approach 1:

The patent introduces a stress relief pattern that segments the molding compound into regions with different mechanical properties. The pattern includes openings that create zones of reduced stress concentration, allowing the thick molding compound to provide protection without causing excessive warping. This segmentation approach divides the uniform structure into functional zones that manage stress distribution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The stress relief pattern implements local quality by creating specific regions with different properties within the molding compound. The patterned openings are strategically placed to provide stress relief exactly where needed, while maintaining the protective function in other areas. This localized modification allows the thick molding compound to coexist with reduced warping.

Inventive Principle:
Principle #3Local quality

2Strength

If a thick layer of molding compound is used, then better protection is provided, but the packaging thickness is increased

Engineering Contradiction:
ImproveprotectionVSAvoidpackaging thickness
Core Design Contradiction:
StrengthVSLength of stationary object

Solution Approach 1:

The stress relief pattern segments the molding compound structure, allowing it to achieve protective function with optimized thickness. By introducing the patterned openings, the material provides equivalent or superior protection with reduced overall thickness, as the pattern itself contributes to structural integrity while relieving stress.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If wafer warpage is reduced, then manufacturing precision is improved, but additional process steps are required

Engineering Contradiction:
Improvewafer warpage controlVSAvoidprocess steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The stress relief pattern is formed as a preliminary structure within the molding compound before final packaging completion. By pre-establishing this pattern, the warpage control is built into the structure beforehand, eliminating the need for additional corrective process steps after molding. The pattern is created during the molding process itself or in preparation for it.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges the stress relief function with the existing molding compound structure. Rather than adding a separate warpage control layer or structure, the stress relief pattern is integrated into the molding compound itself, combining multiple functions (protection, stress relief, and warpage control) into a single component.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively suppresses warpage by distributing stress and maintaining electrical connectivity, enhancing the stability and reliability of semiconductor device packages.

Implementation Method 1

forming a pattern of dielectric material on an active surface of the die to surround a plurality of metal contacts... The dielectric material has a young's modulus lower than a young's modulus of the mold compound

Methodology Applied
Scientific EffectStress distribution:

Implementation Method 2

the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound... results in increased warping of the packaging due to coefficient of thermal expansion (CTE) mismatch

Methodology Applied
Scientific EffectCoefficient of thermal expansion mismatch: Thermal Expansion

Data Source

PatentUS10249573B2Semiconductor device package with a stress relax pattern
Publication Date: 2019.04.02 POWERTECH TECHNOLOGY INC
  • US10249573B2 patent drawing
  • US10249573B2 patent drawing
  • US10249573B2 patent drawing

AI summary

A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically connected to the die and surrounded by the pattern, a mold compound formed around the pattern, the die and the metal contacts, and a redistribution layer formed on a grinded surface of the mold compound and electrically connected to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound.