Semiconductor Element With Stress-Relaxing Layer

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Solution Overview

Problem

Semiconductor devices experience thermal stress and reliability issues due to differences in thermal expansion coefficients between the bump and semiconductor layers, leading to inferior electrical characteristics and increased manufacturing costs from the need for multiple wiring line layers.

Innovation Solution

A semiconductor element with a stress-relaxing layer made of high-melting-point metal between the semiconductor region and the bump, eliminating the need for current paths between conductor patterns and reducing the number of wiring line layers by using the bump to connect terminal electrodes with isolated electrode structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a bump is used to electrically connect multiple terminal electrodes, then the number of wiring line layers is reduced, but thermal stress increases due to difference in thermal expansion coefficient between bump and semiconductor layer

Engineering Contradiction:
Improvenumber of wiring line layersVSAvoidthermal stress
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

A stress-relaxing layer is introduced as an intermediary component between the bump and the semiconductor region. This layer has a thermal expansion coefficient that is closer to that of the semiconductor layer, thereby reducing thermal stress while maintaining the simplified wiring structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The stress-relaxing layer is formed using a composite material structure, specifically a multilayer film including an inorganic film (such as silicon nitride or silicon oxide) and an organic film (such as polyimide). This composite structure provides both stress relaxation and thermal expansion matching properties.

Inventive Principle:
Principle #40Composite materials

2Reliability

If collective wiring lines are used to connect three terminals of multiple unit transistors, then electrical connectivity is achieved, but at least two wiring line layers are required

Engineering Contradiction:
Improveelectrical connectivityVSAvoidnumber of wiring line layers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bump structure is merged with the electrical connection function, serving both as a mechanical support and as an electrical conductor that directly connects multiple terminal electrodes. This eliminates the need for separate wiring line layers to achieve electrical connectivity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bump is designed to perform multiple functions simultaneously: providing mechanical support, dissipating heat, and establishing electrical connections between multiple terminal electrodes. This multi-functionality reduces the overall device complexity by eliminating dedicated wiring layers.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces thermal stress, enhances reliability, and lowers manufacturing costs by eliminating unnecessary wiring layers while maintaining effective heat dissipation and high-frequency characteristics.

Implementation Method 1

thermal stress generated in a semiconductor layer due to a difference in thermal expansion coefficient between the conductive pillar (bump) and the semiconductor layer

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

a stress-relaxing layer that is arranged between the semiconductor region of the transistor and the bump and is composed of a metal material containing a high-melting-point metal

Methodology Applied
Scientific EffectHigh-melting-point metal property:

Data Source

PatentUS10566303B2Semiconductor element
Publication Date: 2020.02.18 MURATA MFG CO LTD
  • US10566303B2 patent drawing
  • US10566303B2 patent drawing
  • US10566303B2 patent drawing

AI summary

A transistor includes a semiconductor region provided on a substrate and three different terminal electrodes. At least one terminal electrode has an isolated electrode structure composed of a plurality of conductor patterns. A bump, which electrically connects the plurality of conductor patterns to each other, is arranged on the terminal electrode having the isolated electrode structure. A stress-relaxing layer, which is composed of a metal material containing a high-melting-point metal, is arranged between the semiconductor region of the transistor and the bump. No current path for connecting the plurality of conductor patterns to each other is arranged between the conductor patterns and the bump.