Semiconductor Die Stress Relieving Layer for Thermal Mismatch
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Solution Overview
Problem
Conventional semiconductor packaging techniques result in tensile stress due to Coefficient of Thermal Expansion (CTE) mismatch between the semiconductor die and the package substrate, leading to cracking, interface delamination, and damage to copper interconnect layers.
Innovation Solution
A stress relieving layer with a predetermined structure and location is integrated into the semiconductor die, having a CTE value greater than the package substrate, to mitigate tensile stress during heating and cooling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging techniques are used to attach semiconductor die to package substrate, then the semiconductor package can be manufactured, but tensile stress causes cracking, interface delamination, or failure in copper interconnect layers
Solution Approach 1:
The patent modifies the physical parameters of the semiconductor die by incorporating a stress relieving layer with specific material properties (different CTE than the silicon die). This layer changes the stress distribution parameters within the die structure, allowing the package to withstand thermal cycling without exceeding the fracture strength of interconnect layers.
Solution Approach 2:
The patent creates a composite structure by integrating a stress relieving layer (made of materials such as silicon nitride, silicon oxide, or polysilicon) into the semiconductor die. This composite approach combines the electrical functionality of the silicon die with the mechanical stress management capabilities of the stress relieving layer, achieving both electrical performance and stress reduction.
2Reliability
If low-k materials are used for insulation of interconnects, then dielectric constant is reduced for better signal performance, but mechanical strength is greatly reduced making it susceptible to cracking and delamination
Solution Approach 1:
The stress relieving layer acts as an intermediary element between the low-k dielectric material and the package substrate. It absorbs and redistributes the tensile stresses that would otherwise be transmitted directly to the weak low-k material, protecting it from cracking and delamination while allowing the low-k material to maintain its excellent electrical insulation properties.
3Strength
If semiconductor die is attached to package substrate with epoxy and heated for curing, then the die is securely bonded, but CTE mismatch causes bending or bowing of the semiconductor die
Solution Approach 1:
The patent explicitly utilizes thermal expansion differences to solve the problem. The stress relieving layer is designed with a CTE higher than that of the silicon die, so during cooling after epoxy curing, this layer expands more than the die, creating a compensating stress that counteracts the bowing caused by the CTE mismatch between the die and package substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress relieving layer effectively reduces wafer bowing and tensile stress, preventing defects such as delamination and cracking in the semiconductor die, thereby enhancing the reliability of the semiconductor package.
Implementation Method 1
the Coefficient of Thermal Expansion (CTE) of the package substrate, such as an organic substrate, is typically larger than the CTE of the silicon wafer of the semiconductor die
Data Source
AI summary
A semiconductor package is provided having reduced tensile stress. The semiconductor package includes a package substrate and a semiconductor die. The semiconductor die is coupled electrically and physically to the package substrate and includes a stress relieving layer incorporated therein. The stress relieving layer has a predetermined structure and a predetermined location within the semiconductor die for reducing tensile stress of the semiconductor package during heating and cooling of the semiconductor package.