Semiconductor Packaging Stress-Relief Structure Design
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Solution Overview
Problem
Semiconductor device packaging substrates face challenges in stress relief, leading to strain and thermal issues due to increasing integration density and smaller component sizes, which can result in reliability problems and reduced performance.
Innovation Solution
Incorporating a stress-relief structure (SRS) with apertures in the solder mask define material in stress-sensitive regions of the substrate, such as corners and edges, to alleviate stress and strain by providing a non-conductive, geometrically varied design that reduces strain values and improves thermal properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased and component size is reduced, then more components can be integrated into a given area, but stress and strain issues worsen leading to reliability problems
Solution Approach 1:
The patent introduces a porous stress relief structure (SRS) with an array of apertures formed in the solder mask define layer. This porous structure allows stress to be distributed and relieved through the aperture regions, preventing stress concentration that would otherwise occur with higher integration densities and smaller components.
Solution Approach 2:
The patent creates a composite structure by combining the solder mask define material with an embedded stress relief structure featuring apertures. This composite design integrates both the protective solder mask function and the stress relief function into a single multi-functional layer, addressing reliability issues while maintaining integration density.
2Reliability
If stress-relief structures are added to alleviate strain, then reliability improves, but device complexity increases
Solution Approach 1:
The patent merges the stress relief function with the existing solder mask define layer by forming the stress relief structure directly within it. This integration eliminates the need for separate stress relief layers or components, reducing overall device complexity while maintaining reliability improvements.
Solution Approach 2:
The stress relief structure is applied locally in specific regions where stress concentration is most problematic, rather than uniformly across the entire substrate. This localized approach provides effective stress relief while minimizing the addition of complex structures to areas that do not require them.
Data Source
AI summary
Packaging structures and methods for semiconductor devices are disclosed. In one embodiment, a substrate for packaging a semiconductor device includes a core substrate, an insulating material disposed over the core substrate, and conductive lines disposed in the insulating material. Contact pads are disposed over the insulating material and the conductive lines. The contact pads are disposed in an integrated circuit mounting region of the core substrate. A solder mask define (SMD) material is disposed over the insulating material. Portions of the contact pads are exposed through openings in the SMD material. A stress-relief structure (SRS) is disposed in the SMD material proximate the contact pads. The SRS is disposed entirely in the integrated circuit mounting region of the core substrate.