Semiconductor Strip Isolation in GAA Transistors for IOFF Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the formation of reliable devices at increasingly smaller sizes, where parasitic channels in gate-all-around (GAA) transistors degrade the off-state current (IOFF) and gate control, leading to performance issues due to the complexity of fabrication processes.
Innovation Solution
An improved process flow for manufacturing GAA transistors involves the use of an isolation layer interposed between the semiconductor strip and the gate structure, and between the semiconductor strip and the source/drain structures, which reduces parasitic leakage current and capacitance, enhancing IOFF and gate control by using materials like SiO2, Si3N4, or air gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity increases and reliability deteriorates
Solution Approach 1:
The patent introduces an isolation layer as an intermediary component between the gate structure and the semiconductor strip. This isolation layer acts as a mediator that reduces parasitic coupling and interference, thereby improving device reliability without requiring changes to the overall scaling approach that drives productivity
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity increases
Solution Approach 1:
The patent segments the gate structure into multiple components including a gate electrode, gate dielectric layer, and isolation layer. This segmentation allows each component to be optimized and fabricated separately using established processes, reducing overall fabrication complexity while maintaining scalability
3Device complexity
If parasitic channels are present in GAA transistors, then device structure is simplified, but off-state current degrades and gate control deteriorates
Solution Approach 1:
The isolation layer serves as an intermediary that blocks parasitic current paths between the gate and semiconductor strip. This intermediary structure effectively eliminates parasitic channels and improves off-state current without significantly complicating the overall transistor architecture
4Device complexity
If parasitic channels are present in GAA transistors, then device structure is simplified, but gate control deteriorates
Solution Approach 1:
The isolation layer acts as an intermediary that electrically isolates the gate structure from parasitic pathways. This mediation enhances gate control by preventing leakage currents that would otherwise interfere with the gate's ability to control the channel effectively
Data Source
AI summary
A semiconductor device includes a substrate, a semiconductor strip, an isolation dielectric, a plurality of channel layers, a gate structure, a plurality of source/drain structures, and an isolation layer. The semiconductor strip extends upwardly from the substrate and has a length extending along a first direction. The isolation dielectric laterally surrounds the semiconductor strip. The channel layers extend in the first direction above the semiconductor strip and arrange in a second direction substantially perpendicular to the substrate. The gate structure surrounds each of the channel layers. The source/drain structures are above the semiconductor strip and on either side of the channel layers. The isolation layer is interposed between the semiconductor strip and the gate structure and further interposed between the semiconductor strip and each of the plurality of source/drain structures.