Semiconductor Material Strips for Stress-Induced Carrier Mobility
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Solution Overview
Problem
Existing methods for stressing semiconductor device channels are expensive and not scalable for large-scale semiconductor device fabrication, particularly those using silicon-germanium layers, which are costly to produce using ultra-high vacuum chemical vapor deposition techniques.
Innovation Solution
Applying and securing semiconductor material strips to a substrate with non-planarities to induce compressive or tensile stress, using oxide islands formed on the substrate to create compression and tension islands that stress the semiconductor material strips, thereby improving carrier mobility without the need for expensive deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon-germanium layers are formed using ultra-high vacuum chemical vapor deposition techniques, then carrier mobility is improved through compressive stress, but manufacturing cost increases significantly
Solution Approach 1:
The patent changes the material composition parameter by using silicon-germanium alloys with varying germanium concentrations (e.g., 5%, 10%, 20%, 30%) to achieve different stress levels. This allows optimization of carrier mobility while controlling manufacturing complexity by selecting appropriate germanium content for specific device requirements
Solution Approach 2:
The patent employs composite structures consisting of silicon-germanium strained layers combined with silicon capping layers. This composite approach enables the silicon-germanium layer to provide compressive stress for improved hole mobility while the silicon capping layer prevents germanium diffusion into the gate oxide, resolving the contradiction between achieving stress and maintaining manufacturing feasibility
2Reliability
If thin silicon-germanium and silicon capping layers are used to generate stress, then carrier mobility improves, but dual-channel characteristics appear at high gate voltages
Solution Approach 1:
The patent applies local quality by creating a graded silicon-germanium layer where the germanium concentration varies through the layer thickness. This grading allows the bottom portion to provide stress while the top portion maintains better interface characteristics, reducing dual-channel effects at high gate voltages while preserving mobility benefits
Solution Approach 2:
The patent uses a silicon capping layer that replicates the crystalline structure and lattice parameters of pure silicon at the interface with the gate oxide. This silicon copy layer prevents germanium atoms from reaching the oxide interface, eliminating the harmful dual-channel characteristics while maintaining the stress-induced mobility improvement in the channel region
3Reliability
If silicon carbide is used to generate tensile strain in NMOS channels, then electron mobility improves, but device complexity increases
Solution Approach 1:
The patent inverts the conventional approach by using tensile strain (instead of compressive strain) in the channel region to improve electron mobility in NMOS devices. This is achieved by applying silicon nitride capping layers that induce tensile stress, reversing the typical compressive stress approach used for PMOS devices and achieving the desired electron mobility enhancement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively stresses semiconductor material strips, enhancing carrier mobility while being economically viable and suitable for large-scale semiconductor device fabrication, improving performance without the high costs associated with traditional techniques.
Implementation Method 1
Applying and securing semiconductor material strips to substrates in such a way as to stress the semiconductor material
Data Source
AI summary
Methods for fabricating semiconductor device structures are disclosed. In some embodiments, methods for fabricating semiconductor device structures may comprising forming at least one raised element on a surface of a substrate, the at least one raised element including sloped sides and a peak, aligning a strip comprising conductive material at least partially over the at least one raised element, and at least partially securing the strip to a surface of the at least one raised element and the surface of the substrate.