Semiconductor Structure with Staged Gate Isolation for Fork Nanosheets
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Solution Overview
Problem
The performance of fork nanosheet devices in semiconductor structures is limited by the difficulty in maintaining accurate spacing and electrical isolation between NMOS and PMOS devices during the manufacturing process, leading to potential connectivity issues and reduced scalability.
Innovation Solution
A semiconductor structure is designed with a first and second isolation structure, where the top of the second isolation structure is lower than the first, allowing for separate formation of gate structures that are electrically connected or isolated, facilitating the creation of different devices on the same substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a dielectric wall is introduced to physically isolate NMOS and PMOS gate grooves, then spacing between devices is reduced and scalability is improved, but manufacturing complexity increases due to additional isolation structure formation steps
Solution Approach 1:
The dielectric wall is formed in advance before gate patterning, physically isolating the NMOS and PMOS gate grooves from each other. This preliminary isolation structure enables subsequent gate formation processes to proceed independently for NMOS and PMOS devices, reducing the minimum spacing requirements between devices while maintaining manufacturing feasibility through staged process implementation
2Reliability
If the top of the second isolation structure is made lower than the first, then gate structures can be separately formed with correct electrical isolation or connection, but structural complexity increases
Solution Approach 1:
The isolation structures are designed with different heights in different regions: the first isolation structure has a higher top surface while the second isolation structure has a lower top surface. This localized height variation enables the first gate structure to be electrically isolated from the second gate structure through the height difference, providing reliable electrical isolation where needed while allowing flexibility in gate formation processes
3Reliability
If fork nanosheet structure is used to improve channel control and drive current, then device performance is enhanced, but difficulty in maintaining accurate spacing and electrical isolation increases
Solution Approach 1:
The dielectric wall acts as an intermediary structure between the NMOS and PMOS fork nanosheet devices. This intermediate element provides physical and electrical isolation, enabling accurate spacing maintenance between the high-performance fork nanosheet structures while simplifying the manufacturing process by preventing unwanted interactions during gate formation
Data Source
AI summary
Semiconductor structure and method of forming semiconductor structure are provided. The semiconductor structure includes a substrate, a first isolation structure, and a first nanostructure and a second nanostructure on two sides of the first isolation structure. The semiconductor structure also includes a second isolation structure, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure. A top of the second isolation structure is lower than a top of the first isolation structure. The semiconductor structure also includes a first gate structure and a second gate structure. The first gate structure and the second gate structure expose a top surface of the first isolation structure. The semiconductor structure also includes a third gate structure and a fourth gate structure. The third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.