Semiconductor Strut Design for Leakage Prevention
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Solution Overview
Problem
The complex fabrication process of semiconductor chips in chip-stack packages, which includes forming insulation, barrier metal, and seed layers, restricts the thickness of the insulation layer, leading to challenges in preventing leakage current and increasing the complexity of the process.
Innovation Solution
A method that forms a semiconductor strut spaced apart from the chip region, eliminating the need for a seed layer, barrier metal layer, and insulation layer, allowing for simplified fabrication and easier control of the gap to prevent leakage current, with the strut serving as an outer connection terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If insulation layer, barrier metal layer, and seed layer are sequentially formed in connection holes, then leakage current is prevented and metal layer adhesion is improved, but fabrication process complexity increases and insulation layer thickness control becomes difficult
Solution Approach 1:
The patent removes the insulation layer, barrier metal layer, and seed layer from the connection hole structure, replacing them with a simplified design where the connection hole is directly filled with metal after basic preparation. This extraction of unnecessary layers reduces fabrication process complexity while maintaining electrical isolation through alternative means.
Solution Approach 2:
The patent changes the parameter of insulation layer thickness by eliminating the need for thick insulation layers. Instead of forming thick insulation layers that are difficult to control, the design uses the semiconductor substrate itself and simplified barrier structures to prevent leakage current, making thickness control feasible.
2Reliability
If insulation layer is formed with sufficient thickness to prevent leakage current, then reliability is improved, but fabrication difficulty increases due to width constraints of connection holes
Solution Approach 1:
The patent transitions from relying on vertical thickness of insulation layers to using horizontal/structural design elements. The connection hole structure is redesigned to utilize the semiconductor substrate geometry and simplified barrier structures, shifting the dimension of leakage prevention from thickness-dependent to geometry-dependent.
Solution Approach 2:
The patent fundamentally changes the parameter approach by eliminating the insulation layer thickness parameter from the design constraints. Instead of optimizing for sufficient thickness, the design uses alternative structural configurations that prevent leakage current without requiring thick layers that are difficult to manufacture.
3Reliability
If conventional multi-layer structure is used in connection holes, then electrical isolation and metal adhesion are achieved, but manufacturing time and process steps increase
Solution Approach 1:
The patent extracts and removes the barrier metal layer and seed layer from the conventional multi-layer connection hole structure, reducing the number of fabrication steps. This simplification maintains electrical isolation functionality while significantly reducing manufacturing time and process complexity.
Solution Approach 2:
The patent merges the functions of multiple layers into a simplified structure. The connection hole preparation process is consolidated to require only essential steps, combining the roles of isolation and adhesion into a more integrated and efficient process that reduces overall fabrication time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, enhances the reliability of semiconductor chips by allowing easier control of the strut's size and features, and improves the prevention of leakage current, resulting in more reliable and efficient chip-stack packages.
Implementation Method 1
patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from a chip region
Implementation Method 2
impurity ions may be doped into the semiconductor strut
Data Source
AI summary
Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.